229 lines
6.1 KiB
C
229 lines
6.1 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* GWIN unit device driver for Marvell AP810 SoC */
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#include <common/debug.h>
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#include <drivers/marvell/gwin.h>
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#include <lib/mmio.h>
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#include <armada_common.h>
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#include <mvebu.h>
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#include <mvebu_def.h>
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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#define DEBUG_ADDR_MAP
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#endif
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/* common defines */
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#define WIN_ENABLE_BIT (0x1)
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#define WIN_TARGET_MASK (0xF)
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#define WIN_TARGET_SHIFT (0x8)
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#define WIN_TARGET(tgt) (((tgt) & WIN_TARGET_MASK) \
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<< WIN_TARGET_SHIFT)
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/* Bits[43:26] of the physical address are the window base,
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* which is aligned to 64MB
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*/
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#define ADDRESS_RSHIFT (26)
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#define ADDRESS_LSHIFT (10)
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#define GWIN_ALIGNMENT_64M (0x4000000)
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/* AP registers */
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#define GWIN_CR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0x0 + \
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(0x10 * (win)))
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#define GWIN_ALR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0x8 + \
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(0x10 * (win)))
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#define GWIN_AHR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0xc + \
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(0x10 * (win)))
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#define CCU_GRU_CR_OFFSET(ap) (MVEBU_CCU_GRU_BASE(ap))
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#define CCR_GRU_CR_GWIN_MBYPASS (1 << 1)
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static void gwin_check(struct addr_map_win *win)
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{
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/* The base is always 64M aligned */
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if (IS_NOT_ALIGN(win->base_addr, GWIN_ALIGNMENT_64M)) {
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win->base_addr &= ~(GWIN_ALIGNMENT_64M - 1);
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NOTICE("%s: Align the base address to 0x%llx\n",
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__func__, win->base_addr);
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}
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/* size parameter validity check */
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if (IS_NOT_ALIGN(win->win_size, GWIN_ALIGNMENT_64M)) {
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win->win_size = ALIGN_UP(win->win_size, GWIN_ALIGNMENT_64M);
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NOTICE("%s: Aligning window size to 0x%llx\n",
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__func__, win->win_size);
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}
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}
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static void gwin_enable_window(int ap_index, struct addr_map_win *win,
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uint32_t win_num)
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{
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uint32_t alr, ahr;
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uint64_t end_addr;
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if ((win->target_id & WIN_TARGET_MASK) != win->target_id) {
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ERROR("target ID = %d, is invalid\n", win->target_id);
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return;
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}
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/* calculate 64bit end-address */
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end_addr = (win->base_addr + win->win_size - 1);
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alr = (uint32_t)((win->base_addr >> ADDRESS_RSHIFT) << ADDRESS_LSHIFT);
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ahr = (uint32_t)((end_addr >> ADDRESS_RSHIFT) << ADDRESS_LSHIFT);
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/* write start address and end address for GWIN */
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mmio_write_32(GWIN_ALR_OFFSET(ap_index, win_num), alr);
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mmio_write_32(GWIN_AHR_OFFSET(ap_index, win_num), ahr);
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/* write the target ID and enable the window */
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mmio_write_32(GWIN_CR_OFFSET(ap_index, win_num),
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WIN_TARGET(win->target_id) | WIN_ENABLE_BIT);
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}
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static void gwin_disable_window(int ap_index, uint32_t win_num)
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{
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uint32_t win_reg;
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win_reg = mmio_read_32(GWIN_CR_OFFSET(ap_index, win_num));
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win_reg &= ~WIN_ENABLE_BIT;
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mmio_write_32(GWIN_CR_OFFSET(ap_index, win_num), win_reg);
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}
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/* Insert/Remove temporary window for using the out-of reset default
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* CPx base address to access the CP configuration space prior to
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* the further base address update in accordance with address mapping
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* design.
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*
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* NOTE: Use the same window array for insertion and removal of
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* temporary windows.
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*/
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void gwin_temp_win_insert(int ap_index, struct addr_map_win *win, int size)
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{
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uint32_t win_id;
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for (int i = 0; i < size; i++) {
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win_id = MVEBU_GWIN_MAX_WINS - i - 1;
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gwin_check(win);
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gwin_enable_window(ap_index, win, win_id);
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win++;
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}
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}
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/*
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* NOTE: Use the same window array for insertion and removal of
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* temporary windows.
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*/
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void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size)
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{
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uint32_t win_id;
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for (int i = 0; i < size; i++) {
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uint64_t base;
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uint32_t target;
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win_id = MVEBU_GWIN_MAX_WINS - i - 1;
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target = mmio_read_32(GWIN_CR_OFFSET(ap_index, win_id));
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target >>= WIN_TARGET_SHIFT;
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target &= WIN_TARGET_MASK;
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base = mmio_read_32(GWIN_ALR_OFFSET(ap_index, win_id));
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base >>= ADDRESS_LSHIFT;
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base <<= ADDRESS_RSHIFT;
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if (win->target_id != target) {
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ERROR("%s: Trying to remove bad window-%d!\n",
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__func__, win_id);
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continue;
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}
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gwin_disable_window(ap_index, win_id);
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win++;
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}
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}
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#ifdef DEBUG_ADDR_MAP
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static void dump_gwin(int ap_index)
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{
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uint32_t win_num;
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/* Dump all GWIN windows */
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printf("\tbank target start end\n");
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printf("\t----------------------------------------------------\n");
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for (win_num = 0; win_num < MVEBU_GWIN_MAX_WINS; win_num++) {
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uint32_t cr;
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uint64_t alr, ahr;
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cr = mmio_read_32(GWIN_CR_OFFSET(ap_index, win_num));
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/* Window enabled */
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if (cr & WIN_ENABLE_BIT) {
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alr = mmio_read_32(GWIN_ALR_OFFSET(ap_index, win_num));
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alr = (alr >> ADDRESS_LSHIFT) << ADDRESS_RSHIFT;
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ahr = mmio_read_32(GWIN_AHR_OFFSET(ap_index, win_num));
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ahr = (ahr >> ADDRESS_LSHIFT) << ADDRESS_RSHIFT;
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printf("\tgwin %d 0x%016llx 0x%016llx\n",
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(cr >> 8) & 0xF, alr, ahr);
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}
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}
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}
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#endif
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int init_gwin(int ap_index)
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{
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struct addr_map_win *win;
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uint32_t win_id;
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uint32_t win_count;
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uint32_t win_reg;
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INFO("Initializing GWIN Address decoding\n");
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/* Get the array of the windows and its size */
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marvell_get_gwin_memory_map(ap_index, &win, &win_count);
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if (win_count <= 0) {
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INFO("no windows configurations found\n");
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return 0;
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}
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if (win_count > MVEBU_GWIN_MAX_WINS) {
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ERROR("number of windows is bigger than %d\n",
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MVEBU_GWIN_MAX_WINS);
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return 0;
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}
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/* disable all windows */
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for (win_id = 0; win_id < MVEBU_GWIN_MAX_WINS; win_id++)
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gwin_disable_window(ap_index, win_id);
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/* enable relevant windows */
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for (win_id = 0; win_id < win_count; win_id++, win++) {
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gwin_check(win);
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gwin_enable_window(ap_index, win, win_id);
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}
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/* GWIN Miss feature has not verified, therefore any access towards
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* remote AP should be accompanied with proper configuration to
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* GWIN registers group and therefore the GWIN Miss feature
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* should be set into Bypass mode, need to make sure all GWIN regions
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* are defined correctly that will assure no GWIN miss occurrance
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* JIRA-AURORA2-1630
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*/
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INFO("Update GWIN miss bypass\n");
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win_reg = mmio_read_32(CCU_GRU_CR_OFFSET(ap_index));
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win_reg |= CCR_GRU_CR_GWIN_MBYPASS;
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mmio_write_32(CCU_GRU_CR_OFFSET(ap_index), win_reg);
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#ifdef DEBUG_ADDR_MAP
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dump_gwin(ap_index);
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#endif
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INFO("Done GWIN Address decoding Initializing\n");
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return 0;
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}
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