975 lines
34 KiB
C
975 lines
34 KiB
C
/*
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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#include "psci_private.h"
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/*
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* SPD power management operations, expected to be supplied by the registered
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* SPD on successful SP initialization
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*/
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const spd_pm_ops_t *psci_spd_pm;
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/*
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* PSCI requested local power state map. This array is used to store the local
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* power states requested by a CPU for power levels from level 1 to
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* PLAT_MAX_PWR_LVL. It does not store the requested local power state for power
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* level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a
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* CPU are the same.
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*
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* During state coordination, the platform is passed an array containing the
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* local states requested for a particular non cpu power domain by each cpu
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* within the domain.
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*
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* TODO: Dense packing of the requested states will cause cache thrashing
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* when multiple power domains write to it. If we allocate the requested
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* states at each power level in a cache-line aligned per-domain memory,
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* the cache thrashing can be avoided.
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*/
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static plat_local_state_t
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psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* Arrays that hold the platform's power domain tree information for state
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* management of power domains.
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* Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain
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* which is an ancestor of a CPU power domain.
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* Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain
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******************************************************************************/
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non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]
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#if USE_COHERENT_MEM
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__section("tzfw_coherent_mem")
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#endif
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;
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/* Lock for PSCI state coordination */
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DEFINE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
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cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* Pointer to functions exported by the platform to complete power mgmt. ops
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******************************************************************************/
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const plat_psci_ops_t *psci_plat_pm_ops;
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/******************************************************************************
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* Check that the maximum power level supported by the platform makes sense
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*****************************************************************************/
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CASSERT((PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL) &&
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(PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL),
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assert_platform_max_pwrlvl_check);
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/*
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* The plat_local_state used by the platform is one of these types: RUN,
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* RETENTION and OFF. The platform can define further sub-states for each type
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* apart from RUN. This categorization is done to verify the sanity of the
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* psci_power_state passed by the platform and to print debug information. The
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* categorization is done on the basis of the following conditions:
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*
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* 1. If (plat_local_state == 0) then the category is STATE_TYPE_RUN.
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*
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* 2. If (0 < plat_local_state <= PLAT_MAX_RET_STATE), then the category is
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* STATE_TYPE_RETN.
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*
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* 3. If (plat_local_state > PLAT_MAX_RET_STATE), then the category is
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* STATE_TYPE_OFF.
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*/
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typedef enum plat_local_state_type {
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STATE_TYPE_RUN = 0,
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STATE_TYPE_RETN,
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STATE_TYPE_OFF
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} plat_local_state_type_t;
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/* Function used to categorize plat_local_state. */
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static plat_local_state_type_t find_local_state_type(plat_local_state_t state)
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{
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if (state != 0U) {
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if (state > PLAT_MAX_RET_STATE) {
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return STATE_TYPE_OFF;
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} else {
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return STATE_TYPE_RETN;
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}
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} else {
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return STATE_TYPE_RUN;
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}
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}
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/******************************************************************************
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* Check that the maximum retention level supported by the platform is less
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* than the maximum off level.
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*****************************************************************************/
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CASSERT(PLAT_MAX_RET_STATE < PLAT_MAX_OFF_STATE,
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assert_platform_max_off_and_retn_state_check);
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/******************************************************************************
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* This function ensures that the power state parameter in a CPU_SUSPEND request
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* is valid. If so, it returns the requested states for each power level.
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*****************************************************************************/
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int psci_validate_power_state(unsigned int power_state,
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psci_power_state_t *state_info)
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{
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/* Check SBZ bits in power state are zero */
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if (psci_check_power_state(power_state) != 0U)
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return PSCI_E_INVALID_PARAMS;
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assert(psci_plat_pm_ops->validate_power_state != NULL);
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/* Validate the power_state using platform pm_ops */
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return psci_plat_pm_ops->validate_power_state(power_state, state_info);
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}
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/******************************************************************************
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* This function retrieves the `psci_power_state_t` for system suspend from
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* the platform.
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*****************************************************************************/
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void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info)
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{
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/*
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* Assert that the required pm_ops hook is implemented to ensure that
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* the capability detected during psci_setup() is valid.
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*/
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assert(psci_plat_pm_ops->get_sys_suspend_power_state != NULL);
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/*
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* Query the platform for the power_state required for system suspend
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*/
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psci_plat_pm_ops->get_sys_suspend_power_state(state_info);
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}
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/*******************************************************************************
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* This function verifies that the all the other cores in the system have been
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* turned OFF and the current CPU is the last running CPU in the system.
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* Returns 1 (true) if the current CPU is the last ON CPU or 0 (false)
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* otherwise.
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******************************************************************************/
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unsigned int psci_is_last_on_cpu(void)
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{
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unsigned int cpu_idx, my_idx = plat_my_core_pos();
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for (cpu_idx = 0; cpu_idx < (unsigned int)PLATFORM_CORE_COUNT;
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cpu_idx++) {
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if (cpu_idx == my_idx) {
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assert(psci_get_aff_info_state() == AFF_STATE_ON);
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continue;
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}
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if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF)
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return 0;
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}
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return 1;
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}
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/*******************************************************************************
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* Routine to return the maximum power level to traverse to after a cpu has
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* been physically powered up. It is expected to be called immediately after
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* reset from assembler code.
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******************************************************************************/
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static unsigned int get_power_on_target_pwrlvl(void)
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{
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unsigned int pwrlvl;
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/*
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* Assume that this cpu was suspended and retrieve its target power
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* level. If it is invalid then it could only have been turned off
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* earlier. PLAT_MAX_PWR_LVL will be the highest power level a
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* cpu can be turned off to.
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*/
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pwrlvl = psci_get_suspend_pwrlvl();
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if (pwrlvl == PSCI_INVALID_PWR_LVL)
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pwrlvl = PLAT_MAX_PWR_LVL;
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assert(pwrlvl < PSCI_INVALID_PWR_LVL);
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return pwrlvl;
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}
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/******************************************************************************
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* Helper function to update the requested local power state array. This array
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* does not store the requested state for the CPU power level. Hence an
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* assertion is added to prevent us from accessing the CPU power level.
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*****************************************************************************/
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static void psci_set_req_local_pwr_state(unsigned int pwrlvl,
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unsigned int cpu_idx,
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plat_local_state_t req_pwr_state)
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{
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assert(pwrlvl > PSCI_CPU_PWR_LVL);
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if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
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(cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) {
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psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
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}
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}
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/******************************************************************************
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* This function initializes the psci_req_local_pwr_states.
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*****************************************************************************/
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void __init psci_init_req_local_pwr_states(void)
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{
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/* Initialize the requested state of all non CPU power domains as OFF */
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unsigned int pwrlvl;
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int core;
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for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) {
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for (core = 0; core < PLATFORM_CORE_COUNT; core++) {
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psci_req_local_pwr_states[pwrlvl][core] =
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PLAT_MAX_OFF_STATE;
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}
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}
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}
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/******************************************************************************
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* Helper function to return a reference to an array containing the local power
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* states requested by each cpu for a power domain at 'pwrlvl'. The size of the
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* array will be the number of cpu power domains of which this power domain is
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* an ancestor. These requested states will be used to determine a suitable
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* target state for this power domain during psci state coordination. An
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* assertion is added to prevent us from accessing the CPU power level.
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*****************************************************************************/
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static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl,
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unsigned int cpu_idx)
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{
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assert(pwrlvl > PSCI_CPU_PWR_LVL);
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if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
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(cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) {
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return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
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} else
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return NULL;
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}
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/*
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* psci_non_cpu_pd_nodes can be placed either in normal memory or coherent
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* memory.
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*
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* With !USE_COHERENT_MEM, psci_non_cpu_pd_nodes is placed in normal memory,
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* it's accessed by both cached and non-cached participants. To serve the common
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* minimum, perform a cache flush before read and after write so that non-cached
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* participants operate on latest data in main memory.
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*
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* When USE_COHERENT_MEM is used, psci_non_cpu_pd_nodes is placed in coherent
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* memory. With HW_ASSISTED_COHERENCY, all PSCI participants are cache-coherent.
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* In both cases, no cache operations are required.
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*/
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/*
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* Retrieve local state of non-CPU power domain node from a non-cached CPU,
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* after any required cache maintenance operation.
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*/
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static plat_local_state_t get_non_cpu_pd_node_local_state(
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unsigned int parent_idx)
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{
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#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
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flush_dcache_range(
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(uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
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sizeof(psci_non_cpu_pd_nodes[parent_idx]));
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#endif
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return psci_non_cpu_pd_nodes[parent_idx].local_state;
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}
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/*
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* Update local state of non-CPU power domain node from a cached CPU; perform
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* any required cache maintenance operation afterwards.
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*/
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static void set_non_cpu_pd_node_local_state(unsigned int parent_idx,
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plat_local_state_t state)
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{
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psci_non_cpu_pd_nodes[parent_idx].local_state = state;
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#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
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flush_dcache_range(
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(uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
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sizeof(psci_non_cpu_pd_nodes[parent_idx]));
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#endif
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}
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/******************************************************************************
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* Helper function to return the current local power state of each power domain
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* from the current cpu power domain to its ancestor at the 'end_pwrlvl'. This
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* function will be called after a cpu is powered on to find the local state
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* each power domain has emerged from.
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*****************************************************************************/
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void psci_get_target_local_pwr_states(unsigned int end_pwrlvl,
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psci_power_state_t *target_state)
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{
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unsigned int parent_idx, lvl;
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plat_local_state_t *pd_state = target_state->pwr_domain_state;
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pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state();
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parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node;
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/* Copy the local power state from node to state_info */
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for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
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pd_state[lvl] = get_non_cpu_pd_node_local_state(parent_idx);
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parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
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}
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/* Set the the higher levels to RUN */
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for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
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target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
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}
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/******************************************************************************
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* Helper function to set the target local power state that each power domain
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* from the current cpu power domain to its ancestor at the 'end_pwrlvl' will
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* enter. This function will be called after coordination of requested power
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* states has been done for each power level.
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*****************************************************************************/
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static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl,
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const psci_power_state_t *target_state)
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{
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unsigned int parent_idx, lvl;
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const plat_local_state_t *pd_state = target_state->pwr_domain_state;
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psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]);
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/*
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* Need to flush as local_state might be accessed with Data Cache
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* disabled during power on
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*/
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psci_flush_cpu_data(psci_svc_cpu_data.local_state);
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parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node;
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/* Copy the local_state from state_info */
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for (lvl = 1U; lvl <= end_pwrlvl; lvl++) {
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set_non_cpu_pd_node_local_state(parent_idx, pd_state[lvl]);
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parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
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}
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}
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/*******************************************************************************
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* PSCI helper function to get the parent nodes corresponding to a cpu_index.
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******************************************************************************/
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void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
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unsigned int end_lvl,
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unsigned int *node_index)
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{
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unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node;
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unsigned int i;
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unsigned int *node = node_index;
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for (i = PSCI_CPU_PWR_LVL + 1U; i <= end_lvl; i++) {
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*node = parent_node;
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node++;
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parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node;
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}
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}
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/******************************************************************************
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* This function is invoked post CPU power up and initialization. It sets the
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* affinity info state, target power state and requested power state for the
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* current CPU and all its ancestor power domains to RUN.
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*****************************************************************************/
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void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl)
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{
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unsigned int parent_idx, cpu_idx = plat_my_core_pos(), lvl;
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parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
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/* Reset the local_state to RUN for the non cpu power domains. */
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for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
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set_non_cpu_pd_node_local_state(parent_idx,
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PSCI_LOCAL_STATE_RUN);
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psci_set_req_local_pwr_state(lvl,
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cpu_idx,
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PSCI_LOCAL_STATE_RUN);
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parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
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}
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/* Set the affinity info state to ON */
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psci_set_aff_info_state(AFF_STATE_ON);
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psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
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psci_flush_cpu_data(psci_svc_cpu_data);
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}
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/******************************************************************************
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* This function is passed the local power states requested for each power
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* domain (state_info) between the current CPU domain and its ancestors until
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* the target power level (end_pwrlvl). It updates the array of requested power
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* states with this information.
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*
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* Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it
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* retrieves the states requested by all the cpus of which the power domain at
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* that level is an ancestor. It passes this information to the platform to
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* coordinate and return the target power state. If the target state for a level
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* is RUN then subsequent levels are not considered. At the CPU level, state
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* coordination is not required. Hence, the requested and the target states are
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* the same.
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*
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* The 'state_info' is updated with the target state for each level between the
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* CPU and the 'end_pwrlvl' and returned to the caller.
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*
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* This function will only be invoked with data cache enabled and while
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* powering down a core.
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*****************************************************************************/
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void psci_do_state_coordination(unsigned int end_pwrlvl,
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psci_power_state_t *state_info)
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{
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unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos();
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unsigned int start_idx;
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unsigned int ncpus;
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plat_local_state_t target_state, *req_states;
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assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
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parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
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/* For level 0, the requested state will be equivalent
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to target state */
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for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
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/* First update the requested power state */
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psci_set_req_local_pwr_state(lvl, cpu_idx,
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state_info->pwr_domain_state[lvl]);
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/* Get the requested power states for this power level */
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start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx;
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req_states = psci_get_req_local_pwr_states(lvl, start_idx);
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/*
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* Let the platform coordinate amongst the requested states at
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* this power level and return the target local power state.
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*/
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ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus;
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target_state = plat_get_target_pwr_state(lvl,
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req_states,
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ncpus);
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state_info->pwr_domain_state[lvl] = target_state;
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/* Break early if the negotiated target power state is RUN */
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if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0)
|
|
break;
|
|
|
|
parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
|
|
}
|
|
|
|
/*
|
|
* This is for cases when we break out of the above loop early because
|
|
* the target power state is RUN at a power level < end_pwlvl.
|
|
* We update the requested power state from state_info and then
|
|
* set the target state as RUN.
|
|
*/
|
|
for (lvl = lvl + 1U; lvl <= end_pwrlvl; lvl++) {
|
|
psci_set_req_local_pwr_state(lvl, cpu_idx,
|
|
state_info->pwr_domain_state[lvl]);
|
|
state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
|
|
|
|
}
|
|
|
|
/* Update the target state in the power domain nodes */
|
|
psci_set_target_local_pwr_states(end_pwrlvl, state_info);
|
|
}
|
|
|
|
/******************************************************************************
|
|
* This function validates a suspend request by making sure that if a standby
|
|
* state is requested then no power level is turned off and the highest power
|
|
* level is placed in a standby/retention state.
|
|
*
|
|
* It also ensures that the state level X will enter is not shallower than the
|
|
* state level X + 1 will enter.
|
|
*
|
|
* This validation will be enabled only for DEBUG builds as the platform is
|
|
* expected to perform these validations as well.
|
|
*****************************************************************************/
|
|
int psci_validate_suspend_req(const psci_power_state_t *state_info,
|
|
unsigned int is_power_down_state)
|
|
{
|
|
unsigned int max_off_lvl, target_lvl, max_retn_lvl;
|
|
plat_local_state_t state;
|
|
plat_local_state_type_t req_state_type, deepest_state_type;
|
|
int i;
|
|
|
|
/* Find the target suspend power level */
|
|
target_lvl = psci_find_target_suspend_lvl(state_info);
|
|
if (target_lvl == PSCI_INVALID_PWR_LVL)
|
|
return PSCI_E_INVALID_PARAMS;
|
|
|
|
/* All power domain levels are in a RUN state to begin with */
|
|
deepest_state_type = STATE_TYPE_RUN;
|
|
|
|
for (i = (int) target_lvl; i >= (int) PSCI_CPU_PWR_LVL; i--) {
|
|
state = state_info->pwr_domain_state[i];
|
|
req_state_type = find_local_state_type(state);
|
|
|
|
/*
|
|
* While traversing from the highest power level to the lowest,
|
|
* the state requested for lower levels has to be the same or
|
|
* deeper i.e. equal to or greater than the state at the higher
|
|
* levels. If this condition is true, then the requested state
|
|
* becomes the deepest state encountered so far.
|
|
*/
|
|
if (req_state_type < deepest_state_type)
|
|
return PSCI_E_INVALID_PARAMS;
|
|
deepest_state_type = req_state_type;
|
|
}
|
|
|
|
/* Find the highest off power level */
|
|
max_off_lvl = psci_find_max_off_lvl(state_info);
|
|
|
|
/* The target_lvl is either equal to the max_off_lvl or max_retn_lvl */
|
|
max_retn_lvl = PSCI_INVALID_PWR_LVL;
|
|
if (target_lvl != max_off_lvl)
|
|
max_retn_lvl = target_lvl;
|
|
|
|
/*
|
|
* If this is not a request for a power down state then max off level
|
|
* has to be invalid and max retention level has to be a valid power
|
|
* level.
|
|
*/
|
|
if ((is_power_down_state == 0U) &&
|
|
((max_off_lvl != PSCI_INVALID_PWR_LVL) ||
|
|
(max_retn_lvl == PSCI_INVALID_PWR_LVL)))
|
|
return PSCI_E_INVALID_PARAMS;
|
|
|
|
return PSCI_E_SUCCESS;
|
|
}
|
|
|
|
/******************************************************************************
|
|
* This function finds the highest power level which will be powered down
|
|
* amongst all the power levels specified in the 'state_info' structure
|
|
*****************************************************************************/
|
|
unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info)
|
|
{
|
|
int i;
|
|
|
|
for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) {
|
|
if (is_local_state_off(state_info->pwr_domain_state[i]) != 0)
|
|
return (unsigned int) i;
|
|
}
|
|
|
|
return PSCI_INVALID_PWR_LVL;
|
|
}
|
|
|
|
/******************************************************************************
|
|
* This functions finds the level of the highest power domain which will be
|
|
* placed in a low power state during a suspend operation.
|
|
*****************************************************************************/
|
|
unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info)
|
|
{
|
|
int i;
|
|
|
|
for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) {
|
|
if (is_local_state_run(state_info->pwr_domain_state[i]) == 0)
|
|
return (unsigned int) i;
|
|
}
|
|
|
|
return PSCI_INVALID_PWR_LVL;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* This function is passed the highest level in the topology tree that the
|
|
* operation should be applied to and a list of node indexes. It picks up locks
|
|
* from the node index list in order of increasing power domain level in the
|
|
* range specified.
|
|
******************************************************************************/
|
|
void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl,
|
|
const unsigned int *parent_nodes)
|
|
{
|
|
unsigned int parent_idx;
|
|
unsigned int level;
|
|
|
|
/* No locking required for level 0. Hence start locking from level 1 */
|
|
for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) {
|
|
parent_idx = parent_nodes[level - 1U];
|
|
psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]);
|
|
}
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* This function is passed the highest level in the topology tree that the
|
|
* operation should be applied to and a list of node indexes. It releases the
|
|
* locks in order of decreasing power domain level in the range specified.
|
|
******************************************************************************/
|
|
void psci_release_pwr_domain_locks(unsigned int end_pwrlvl,
|
|
const unsigned int *parent_nodes)
|
|
{
|
|
unsigned int parent_idx;
|
|
unsigned int level;
|
|
|
|
/* Unlock top down. No unlocking required for level 0. */
|
|
for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1U; level--) {
|
|
parent_idx = parent_nodes[level - 1U];
|
|
psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]);
|
|
}
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Simple routine to determine whether a mpidr is valid or not.
|
|
******************************************************************************/
|
|
int psci_validate_mpidr(u_register_t mpidr)
|
|
{
|
|
if (plat_core_pos_by_mpidr(mpidr) < 0)
|
|
return PSCI_E_INVALID_PARAMS;
|
|
|
|
return PSCI_E_SUCCESS;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* This function determines the full entrypoint information for the requested
|
|
* PSCI entrypoint on power on/resume and returns it.
|
|
******************************************************************************/
|
|
#ifdef __aarch64__
|
|
static int psci_get_ns_ep_info(entry_point_info_t *ep,
|
|
uintptr_t entrypoint,
|
|
u_register_t context_id)
|
|
{
|
|
u_register_t ep_attr, sctlr;
|
|
unsigned int daif, ee, mode;
|
|
u_register_t ns_scr_el3 = read_scr_el3();
|
|
u_register_t ns_sctlr_el1 = read_sctlr_el1();
|
|
|
|
sctlr = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ?
|
|
read_sctlr_el2() : ns_sctlr_el1;
|
|
ee = 0;
|
|
|
|
ep_attr = NON_SECURE | EP_ST_DISABLE;
|
|
if ((sctlr & SCTLR_EE_BIT) != 0U) {
|
|
ep_attr |= EP_EE_BIG;
|
|
ee = 1;
|
|
}
|
|
SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
|
|
|
|
ep->pc = entrypoint;
|
|
zeromem(&ep->args, sizeof(ep->args));
|
|
ep->args.arg0 = context_id;
|
|
|
|
/*
|
|
* Figure out whether the cpu enters the non-secure address space
|
|
* in aarch32 or aarch64
|
|
*/
|
|
if ((ns_scr_el3 & SCR_RW_BIT) != 0U) {
|
|
|
|
/*
|
|
* Check whether a Thumb entry point has been provided for an
|
|
* aarch64 EL
|
|
*/
|
|
if ((entrypoint & 0x1UL) != 0UL)
|
|
return PSCI_E_INVALID_ADDRESS;
|
|
|
|
mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? MODE_EL2 : MODE_EL1;
|
|
|
|
ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
|
|
} else {
|
|
|
|
mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ?
|
|
MODE32_hyp : MODE32_svc;
|
|
|
|
/*
|
|
* TODO: Choose async. exception bits if HYP mode is not
|
|
* implemented according to the values of SCR.{AW, FW} bits
|
|
*/
|
|
daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
|
|
|
|
ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif);
|
|
}
|
|
|
|
return PSCI_E_SUCCESS;
|
|
}
|
|
#else /* !__aarch64__ */
|
|
static int psci_get_ns_ep_info(entry_point_info_t *ep,
|
|
uintptr_t entrypoint,
|
|
u_register_t context_id)
|
|
{
|
|
u_register_t ep_attr;
|
|
unsigned int aif, ee, mode;
|
|
u_register_t scr = read_scr();
|
|
u_register_t ns_sctlr, sctlr;
|
|
|
|
/* Switch to non secure state */
|
|
write_scr(scr | SCR_NS_BIT);
|
|
isb();
|
|
ns_sctlr = read_sctlr();
|
|
|
|
sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr;
|
|
|
|
/* Return to original state */
|
|
write_scr(scr);
|
|
isb();
|
|
ee = 0;
|
|
|
|
ep_attr = NON_SECURE | EP_ST_DISABLE;
|
|
if (sctlr & SCTLR_EE_BIT) {
|
|
ep_attr |= EP_EE_BIG;
|
|
ee = 1;
|
|
}
|
|
SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
|
|
|
|
ep->pc = entrypoint;
|
|
zeromem(&ep->args, sizeof(ep->args));
|
|
ep->args.arg0 = context_id;
|
|
|
|
mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc;
|
|
|
|
/*
|
|
* TODO: Choose async. exception bits if HYP mode is not
|
|
* implemented according to the values of SCR.{AW, FW} bits
|
|
*/
|
|
aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT;
|
|
|
|
ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif);
|
|
|
|
return PSCI_E_SUCCESS;
|
|
}
|
|
|
|
#endif /* __aarch64__ */
|
|
|
|
/*******************************************************************************
|
|
* This function validates the entrypoint with the platform layer if the
|
|
* appropriate pm_ops hook is exported by the platform and returns the
|
|
* 'entry_point_info'.
|
|
******************************************************************************/
|
|
int psci_validate_entry_point(entry_point_info_t *ep,
|
|
uintptr_t entrypoint,
|
|
u_register_t context_id)
|
|
{
|
|
int rc;
|
|
|
|
/* Validate the entrypoint using platform psci_ops */
|
|
if (psci_plat_pm_ops->validate_ns_entrypoint != NULL) {
|
|
rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint);
|
|
if (rc != PSCI_E_SUCCESS)
|
|
return PSCI_E_INVALID_ADDRESS;
|
|
}
|
|
|
|
/*
|
|
* Verify and derive the re-entry information for
|
|
* the non-secure world from the non-secure state from
|
|
* where this call originated.
|
|
*/
|
|
rc = psci_get_ns_ep_info(ep, entrypoint, context_id);
|
|
return rc;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Generic handler which is called when a cpu is physically powered on. It
|
|
* traverses the node information and finds the highest power level powered
|
|
* off and performs generic, architectural, platform setup and state management
|
|
* to power on that power level and power levels below it.
|
|
* e.g. For a cpu that's been powered on, it will call the platform specific
|
|
* code to enable the gic cpu interface and for a cluster it will enable
|
|
* coherency at the interconnect level in addition to gic cpu interface.
|
|
******************************************************************************/
|
|
void psci_warmboot_entrypoint(void)
|
|
{
|
|
unsigned int end_pwrlvl;
|
|
unsigned int cpu_idx = plat_my_core_pos();
|
|
unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
|
|
psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
|
|
|
|
/*
|
|
* Verify that we have been explicitly turned ON or resumed from
|
|
* suspend.
|
|
*/
|
|
if (psci_get_aff_info_state() == AFF_STATE_OFF) {
|
|
ERROR("Unexpected affinity info state");
|
|
panic();
|
|
}
|
|
|
|
/*
|
|
* Get the maximum power domain level to traverse to after this cpu
|
|
* has been physically powered up.
|
|
*/
|
|
end_pwrlvl = get_power_on_target_pwrlvl();
|
|
|
|
/* Get the parent nodes */
|
|
psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes);
|
|
|
|
/*
|
|
* This function acquires the lock corresponding to each power level so
|
|
* that by the time all locks are taken, the system topology is snapshot
|
|
* and state management can be done safely.
|
|
*/
|
|
psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes);
|
|
|
|
psci_get_target_local_pwr_states(end_pwrlvl, &state_info);
|
|
|
|
#if ENABLE_PSCI_STAT
|
|
plat_psci_stat_accounting_stop(&state_info);
|
|
#endif
|
|
|
|
/*
|
|
* This CPU could be resuming from suspend or it could have just been
|
|
* turned on. To distinguish between these 2 cases, we examine the
|
|
* affinity state of the CPU:
|
|
* - If the affinity state is ON_PENDING then it has just been
|
|
* turned on.
|
|
* - Else it is resuming from suspend.
|
|
*
|
|
* Depending on the type of warm reset identified, choose the right set
|
|
* of power management handler and perform the generic, architecture
|
|
* and platform specific handling.
|
|
*/
|
|
if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING)
|
|
psci_cpu_on_finish(cpu_idx, &state_info);
|
|
else
|
|
psci_cpu_suspend_finish(cpu_idx, &state_info);
|
|
|
|
/*
|
|
* Set the requested and target state of this CPU and all the higher
|
|
* power domains which are ancestors of this CPU to run.
|
|
*/
|
|
psci_set_pwr_domains_to_run(end_pwrlvl);
|
|
|
|
#if ENABLE_PSCI_STAT
|
|
/*
|
|
* Update PSCI stats.
|
|
* Caches are off when writing stats data on the power down path.
|
|
* Since caches are now enabled, it's necessary to do cache
|
|
* maintenance before reading that same data.
|
|
*/
|
|
psci_stats_update_pwr_up(end_pwrlvl, &state_info);
|
|
#endif
|
|
|
|
/*
|
|
* This loop releases the lock corresponding to each power level
|
|
* in the reverse order to which they were acquired.
|
|
*/
|
|
psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes);
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* This function initializes the set of hooks that PSCI invokes as part of power
|
|
* management operation. The power management hooks are expected to be provided
|
|
* by the SPD, after it finishes all its initialization
|
|
******************************************************************************/
|
|
void psci_register_spd_pm_hook(const spd_pm_ops_t *pm)
|
|
{
|
|
assert(pm != NULL);
|
|
psci_spd_pm = pm;
|
|
|
|
if (pm->svc_migrate != NULL)
|
|
psci_caps |= define_psci_cap(PSCI_MIG_AARCH64);
|
|
|
|
if (pm->svc_migrate_info != NULL)
|
|
psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64)
|
|
| define_psci_cap(PSCI_MIG_INFO_TYPE);
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* This function invokes the migrate info hook in the spd_pm_ops. It performs
|
|
* the necessary return value validation. If the Secure Payload is UP and
|
|
* migrate capable, it returns the mpidr of the CPU on which the Secure payload
|
|
* is resident through the mpidr parameter. Else the value of the parameter on
|
|
* return is undefined.
|
|
******************************************************************************/
|
|
int psci_spd_migrate_info(u_register_t *mpidr)
|
|
{
|
|
int rc;
|
|
|
|
if ((psci_spd_pm == NULL) || (psci_spd_pm->svc_migrate_info == NULL))
|
|
return PSCI_E_NOT_SUPPORTED;
|
|
|
|
rc = psci_spd_pm->svc_migrate_info(mpidr);
|
|
|
|
assert((rc == PSCI_TOS_UP_MIG_CAP) || (rc == PSCI_TOS_NOT_UP_MIG_CAP) ||
|
|
(rc == PSCI_TOS_NOT_PRESENT_MP) || (rc == PSCI_E_NOT_SUPPORTED));
|
|
|
|
return rc;
|
|
}
|
|
|
|
|
|
/*******************************************************************************
|
|
* This function prints the state of all power domains present in the
|
|
* system
|
|
******************************************************************************/
|
|
void psci_print_power_domain_map(void)
|
|
{
|
|
#if LOG_LEVEL >= LOG_LEVEL_INFO
|
|
int idx;
|
|
plat_local_state_t state;
|
|
plat_local_state_type_t state_type;
|
|
|
|
/* This array maps to the PSCI_STATE_X definitions in psci.h */
|
|
static const char * const psci_state_type_str[] = {
|
|
"ON",
|
|
"RETENTION",
|
|
"OFF",
|
|
};
|
|
|
|
INFO("PSCI Power Domain Map:\n");
|
|
for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT);
|
|
idx++) {
|
|
state_type = find_local_state_type(
|
|
psci_non_cpu_pd_nodes[idx].local_state);
|
|
INFO(" Domain Node : Level %u, parent_node %d,"
|
|
" State %s (0x%x)\n",
|
|
psci_non_cpu_pd_nodes[idx].level,
|
|
psci_non_cpu_pd_nodes[idx].parent_node,
|
|
psci_state_type_str[state_type],
|
|
psci_non_cpu_pd_nodes[idx].local_state);
|
|
}
|
|
|
|
for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) {
|
|
state = psci_get_cpu_local_state_by_idx(idx);
|
|
state_type = find_local_state_type(state);
|
|
INFO(" CPU Node : MPID 0x%llx, parent_node %d,"
|
|
" State %s (0x%x)\n",
|
|
(unsigned long long)psci_cpu_pd_nodes[idx].mpidr,
|
|
psci_cpu_pd_nodes[idx].parent_node,
|
|
psci_state_type_str[state_type],
|
|
psci_get_cpu_local_state_by_idx(idx));
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Return whether any secondaries were powered up with CPU_ON call. A CPU that
|
|
* have ever been powered up would have set its MPDIR value to something other
|
|
* than PSCI_INVALID_MPIDR. Note that MPDIR isn't reset back to
|
|
* PSCI_INVALID_MPIDR when a CPU is powered down later, so the return value is
|
|
* meaningful only when called on the primary CPU during early boot.
|
|
*****************************************************************************/
|
|
int psci_secondaries_brought_up(void)
|
|
{
|
|
unsigned int idx, n_valid = 0U;
|
|
|
|
for (idx = 0U; idx < ARRAY_SIZE(psci_cpu_pd_nodes); idx++) {
|
|
if (psci_cpu_pd_nodes[idx].mpidr != PSCI_INVALID_MPIDR)
|
|
n_valid++;
|
|
}
|
|
|
|
assert(n_valid > 0U);
|
|
|
|
return (n_valid > 1U) ? 1 : 0;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Initiate power down sequence, by calling power down operations registered for
|
|
* this CPU.
|
|
******************************************************************************/
|
|
void psci_do_pwrdown_sequence(unsigned int power_level)
|
|
{
|
|
#if HW_ASSISTED_COHERENCY
|
|
/*
|
|
* With hardware-assisted coherency, the CPU drivers only initiate the
|
|
* power down sequence, without performing cache-maintenance operations
|
|
* in software. Data caches enabled both before and after this call.
|
|
*/
|
|
prepare_cpu_pwr_dwn(power_level);
|
|
#else
|
|
/*
|
|
* Without hardware-assisted coherency, the CPU drivers disable data
|
|
* caches, then perform cache-maintenance operations in software.
|
|
*
|
|
* This also calls prepare_cpu_pwr_dwn() to initiate power down
|
|
* sequence, but that function will return with data caches disabled.
|
|
* We must ensure that the stack memory is flushed out to memory before
|
|
* we start popping from it again.
|
|
*/
|
|
psci_do_pwrdown_cache_maintenance(power_level);
|
|
#endif
|
|
}
|