302 lines
11 KiB
C
302 lines
11 KiB
C
/*
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stddef.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <context.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/cpus/errata_report.h>
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#include <plat/common/platform.h>
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#include "psci_private.h"
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/*******************************************************************************
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* Per cpu non-secure contexts used to program the architectural state prior
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* return to the normal world.
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* TODO: Use the memory allocator to set aside memory for the contexts instead
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* of relying on platform defined constants.
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******************************************************************************/
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static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT];
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/******************************************************************************
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* Define the psci capability variable.
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*****************************************************************************/
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unsigned int psci_caps;
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/*******************************************************************************
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* Function which initializes the 'psci_non_cpu_pd_nodes' or the
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* 'psci_cpu_pd_nodes' corresponding to the power level.
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******************************************************************************/
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static void __init psci_init_pwr_domain_node(unsigned char node_idx,
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unsigned int parent_idx,
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unsigned char level)
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{
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if (level > PSCI_CPU_PWR_LVL) {
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psci_non_cpu_pd_nodes[node_idx].level = level;
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psci_lock_init(psci_non_cpu_pd_nodes, node_idx);
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psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx;
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psci_non_cpu_pd_nodes[node_idx].local_state =
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PLAT_MAX_OFF_STATE;
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} else {
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psci_cpu_data_t *svc_cpu_data;
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psci_cpu_pd_nodes[node_idx].parent_node = parent_idx;
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/* Initialize with an invalid mpidr */
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psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR;
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svc_cpu_data =
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&(_cpu_data_by_index(node_idx)->psci_svc_cpu_data);
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/* Set the Affinity Info for the cores as OFF */
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svc_cpu_data->aff_info_state = AFF_STATE_OFF;
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/* Invalidate the suspend level for the cpu */
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svc_cpu_data->target_pwrlvl = PSCI_INVALID_PWR_LVL;
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/* Set the power state to OFF state */
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svc_cpu_data->local_state = PLAT_MAX_OFF_STATE;
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psci_flush_dcache_range((uintptr_t)svc_cpu_data,
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sizeof(*svc_cpu_data));
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cm_set_context_by_index(node_idx,
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(void *) &psci_ns_context[node_idx],
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NON_SECURE);
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}
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}
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/*******************************************************************************
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* This functions updates cpu_start_idx and ncpus field for each of the node in
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* psci_non_cpu_pd_nodes[]. It does so by comparing the parent nodes of each of
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* the CPUs and check whether they match with the parent of the previous
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* CPU. The basic assumption for this work is that children of the same parent
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* are allocated adjacent indices. The platform should ensure this though proper
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* mapping of the CPUs to indices via plat_core_pos_by_mpidr() and
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* plat_my_core_pos() APIs.
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*******************************************************************************/
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static void __init psci_update_pwrlvl_limits(void)
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{
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int j, cpu_idx;
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unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0};
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unsigned int temp_index[PLAT_MAX_PWR_LVL];
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for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) {
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psci_get_parent_pwr_domain_nodes(cpu_idx,
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(unsigned int)PLAT_MAX_PWR_LVL,
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temp_index);
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for (j = (int) PLAT_MAX_PWR_LVL - 1; j >= 0; j--) {
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if (temp_index[j] != nodes_idx[j]) {
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nodes_idx[j] = temp_index[j];
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psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx
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= cpu_idx;
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}
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psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++;
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}
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}
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}
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/*******************************************************************************
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* Core routine to populate the power domain tree. The tree descriptor passed by
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* the platform is populated breadth-first and the first entry in the map
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* informs the number of root power domains. The parent nodes of the root nodes
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* will point to an invalid entry(-1).
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******************************************************************************/
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static void __init populate_power_domain_tree(const unsigned char *topology)
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{
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unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl;
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unsigned int node_index = 0U, num_children;
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int parent_node_index = 0;
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int level = (int) PLAT_MAX_PWR_LVL;
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/*
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* For each level the inputs are:
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* - number of nodes at this level in plat_array i.e. num_nodes_at_level
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* This is the sum of values of nodes at the parent level.
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* - Index of first entry at this level in the plat_array i.e.
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* parent_node_index.
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* - Index of first free entry in psci_non_cpu_pd_nodes[] or
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* psci_cpu_pd_nodes[] i.e. node_index depending upon the level.
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*/
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while (level >= (int) PSCI_CPU_PWR_LVL) {
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num_nodes_at_next_lvl = 0U;
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/*
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* For each entry (parent node) at this level in the plat_array:
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* - Find the number of children
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* - Allocate a node in a power domain array for each child
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* - Set the parent of the child to the parent_node_index - 1
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* - Increment parent_node_index to point to the next parent
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* - Accumulate the number of children at next level.
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*/
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for (i = 0U; i < num_nodes_at_lvl; i++) {
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assert(parent_node_index <=
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PSCI_NUM_NON_CPU_PWR_DOMAINS);
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num_children = topology[parent_node_index];
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for (j = node_index;
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j < (node_index + num_children); j++)
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psci_init_pwr_domain_node((unsigned char)j,
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parent_node_index - 1,
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(unsigned char)level);
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node_index = j;
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num_nodes_at_next_lvl += num_children;
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parent_node_index++;
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}
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num_nodes_at_lvl = num_nodes_at_next_lvl;
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level--;
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/* Reset the index for the cpu power domain array */
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if (level == (int) PSCI_CPU_PWR_LVL)
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node_index = 0;
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}
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/* Validate the sanity of array exported by the platform */
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assert((int) j == PLATFORM_CORE_COUNT);
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}
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/*******************************************************************************
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* This function does the architectural setup and takes the warm boot
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* entry-point `mailbox_ep` as an argument. The function also initializes the
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* power domain topology tree by querying the platform. The power domain nodes
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* higher than the CPU are populated in the array psci_non_cpu_pd_nodes[] and
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* the CPU power domains are populated in psci_cpu_pd_nodes[]. The platform
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* exports its static topology map through the
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* populate_power_domain_topology_tree() API. The algorithm populates the
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* psci_non_cpu_pd_nodes and psci_cpu_pd_nodes iteratively by using this
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* topology map. On a platform that implements two clusters of 2 cpus each,
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* and supporting 3 domain levels, the populated psci_non_cpu_pd_nodes would
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* look like this:
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*
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* ---------------------------------------------------
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* | system node | cluster 0 node | cluster 1 node |
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* ---------------------------------------------------
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*
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* And populated psci_cpu_pd_nodes would look like this :
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* <- cpus cluster0 -><- cpus cluster1 ->
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* ------------------------------------------------
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* | CPU 0 | CPU 1 | CPU 2 | CPU 3 |
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* ------------------------------------------------
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******************************************************************************/
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int __init psci_setup(const psci_lib_args_t *lib_args)
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{
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const unsigned char *topology_tree;
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assert(VERIFY_PSCI_LIB_ARGS_V1(lib_args));
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/* Do the Architectural initialization */
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psci_arch_setup();
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/* Query the topology map from the platform */
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topology_tree = plat_get_power_domain_tree_desc();
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/* Populate the power domain arrays using the platform topology map */
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populate_power_domain_tree(topology_tree);
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/* Update the CPU limits for each node in psci_non_cpu_pd_nodes */
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psci_update_pwrlvl_limits();
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/* Populate the mpidr field of cpu node for this CPU */
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psci_cpu_pd_nodes[plat_my_core_pos()].mpidr =
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read_mpidr() & MPIDR_AFFINITY_MASK;
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psci_init_req_local_pwr_states();
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/*
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* Set the requested and target state of this CPU and all the higher
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* power domain levels for this CPU to run.
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*/
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psci_set_pwr_domains_to_run(PLAT_MAX_PWR_LVL);
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(void) plat_setup_psci_ops((uintptr_t)lib_args->mailbox_ep,
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&psci_plat_pm_ops);
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assert(psci_plat_pm_ops != NULL);
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/*
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* Flush `psci_plat_pm_ops` as it will be accessed by secondary CPUs
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* during warm boot, possibly before data cache is enabled.
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*/
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psci_flush_dcache_range((uintptr_t)&psci_plat_pm_ops,
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sizeof(psci_plat_pm_ops));
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/* Initialize the psci capability */
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psci_caps = PSCI_GENERIC_CAP;
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if (psci_plat_pm_ops->pwr_domain_off != NULL)
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psci_caps |= define_psci_cap(PSCI_CPU_OFF);
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if ((psci_plat_pm_ops->pwr_domain_on != NULL) &&
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(psci_plat_pm_ops->pwr_domain_on_finish != NULL))
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psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64);
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if ((psci_plat_pm_ops->pwr_domain_suspend != NULL) &&
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(psci_plat_pm_ops->pwr_domain_suspend_finish != NULL)) {
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psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64);
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if (psci_plat_pm_ops->get_sys_suspend_power_state != NULL)
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psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64);
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}
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if (psci_plat_pm_ops->system_off != NULL)
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psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF);
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if (psci_plat_pm_ops->system_reset != NULL)
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psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET);
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if (psci_plat_pm_ops->get_node_hw_state != NULL)
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psci_caps |= define_psci_cap(PSCI_NODE_HW_STATE_AARCH64);
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if ((psci_plat_pm_ops->read_mem_protect != NULL) &&
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(psci_plat_pm_ops->write_mem_protect != NULL))
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psci_caps |= define_psci_cap(PSCI_MEM_PROTECT);
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if (psci_plat_pm_ops->mem_protect_chk != NULL)
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psci_caps |= define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64);
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if (psci_plat_pm_ops->system_reset2 != NULL)
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psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64);
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#if ENABLE_PSCI_STAT
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psci_caps |= define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64);
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psci_caps |= define_psci_cap(PSCI_STAT_COUNT_AARCH64);
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#endif
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return 0;
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}
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/*******************************************************************************
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* This duplicates what the primary cpu did after a cold boot in BL1. The same
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* needs to be done when a cpu is hotplugged in. This function could also over-
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* ride any EL3 setup done by BL1 as this code resides in rw memory.
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******************************************************************************/
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void psci_arch_setup(void)
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{
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#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
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/* Program the counter frequency */
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write_cntfrq_el0(plat_get_syscnt_freq2());
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#endif
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/* Initialize the cpu_ops pointer. */
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init_cpu_ops();
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/* Having initialized cpu_ops, we can now print errata status */
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print_errata_status();
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#if ENABLE_PAUTH
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/* Store APIAKey_EL1 key */
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set_cpu_data(apiakey[0], read_apiakeylo_el1());
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set_cpu_data(apiakey[1], read_apiakeyhi_el1());
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#endif /* ENABLE_PAUTH */
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}
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/******************************************************************************
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* PSCI Library interface to initialize the cpu context for the next non
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* secure image during cold boot. The relevant registers in the cpu context
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* need to be retrieved and programmed on return from this interface.
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*****************************************************************************/
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void psci_prepare_next_non_secure_ctx(entry_point_info_t *next_image_info)
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{
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assert(GET_SECURITY_STATE(next_image_info->h.attr) == NON_SECURE);
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cm_init_my_context(next_image_info);
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cm_prepare_el3_exit(NON_SECURE);
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}
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