106 lines
3.4 KiB
C
106 lines
3.4 KiB
C
/*
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* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __EC_BOARD_CR50_SCRATCH_REG1_H
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#define __EC_BOARD_CR50_SCRATCH_REG1_H
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/*
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* Bit assignments of the LONG_LIFE_SCRATCH1 register. This register survives
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* all kinds of resets, it is cleared only on the Power ON event.
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*/
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#define BOARD_SLAVE_CONFIG_SPI BIT(0) /* TPM uses SPI interface */
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#define BOARD_SLAVE_CONFIG_I2C BIT(1) /* TPM uses I2C interface */
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/*
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* The gaps are left to ensure backwards compatibility with the earliest cr50
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* code releases. It will be possible to safely reuse these gaps if and when the
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* rest of the bits are taken.
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*/
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/* TODO(crosbug.com/p/56945): Remove when sys_rst_l has an external pullup */
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#define BOARD_NEEDS_SYS_RST_PULL_UP BIT(5) /* Add a pullup to sys_rst_l */
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#define BOARD_USE_PLT_RESET BIT(6) /* Use plt_rst_l instead of */
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/* sys_rst_l to monitor the */
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/* system resets */
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/* Bits to store write protect bit state across deep sleep and resets. */
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#define BOARD_WP_ASSERTED BIT(8)
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#define BOARD_FORCING_WP BIT(9)
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/*
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* Bit to signal to compatible RO to suppress its uart output.
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* Helps to reduce time to resume from deep sleep.
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*/
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#define BOARD_NO_RO_UART BIT(10)
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/*
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* Bits to store current case-closed debug state across deep sleep.
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*
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* DO NOT examine these bits to determine the current CCD state. Call methods
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* from case_closed_debug.h instead.
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*/
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#define BOARD_CCD_SHIFT 11
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#define BOARD_CCD_STATE (3 << BOARD_CCD_SHIFT)
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/* Prevent Cr50 from entering deep sleep when the AP is off */
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#define BOARD_DEEP_SLEEP_DISABLED BIT(13)
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/* Use Cr50_RX_AP_TX to determine if the AP is off or on */
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#define BOARD_DETECT_AP_WITH_UART BIT(14)
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/* ITE EC sync sequence generation after reset is required. */
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#define BOARD_ITE_EC_SYNC_NEEDED BIT(15)
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/*
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* Enable delayed write protect disable for systems that can be opened
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* in less than 2 minutes
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*/
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#define BOARD_WP_DISABLE_DELAY BIT(16)
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/*
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* Enable custom options required for the closed source EC on the
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* Sarien/Arcada boards. Includes the following behavior
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* Enable factory mode to closed-source EC via GPIO
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* Support customer diagnostic mode
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* UEFI factory mode
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* EC extended reset
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* Power+Refresh recovery mode (instead of Power+Refresh+Esc)
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*/
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#define BOARD_CLOSED_SOURCE_SET1 BIT(17)
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/*
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* Wait until PLT_RST_L is asserted before deasserting reset.
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*/
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#define BOARD_CLOSED_LOOP_RESET BIT(18)
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/*
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* The board uses INA pins as GPIOs, so it can't support reading inas using usb
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* i2c.
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*/
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#define BOARD_NO_INA_SUPPORT BIT(19)
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/*
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* The board allows commands to stop TPM (Wilco, Campfire, etc.)
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*/
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#define BOARD_ALLOW_CHANGE_TPM_MODE BIT(20)
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/*
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* Macro to capture all properties related to board strapping pins. This must be
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* updated if additional strap related properties are added.
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*/
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#define BOARD_ALL_PROPERTIES ( \
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BOARD_ALLOW_CHANGE_TPM_MODE | \
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BOARD_CLOSED_LOOP_RESET | \
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BOARD_CLOSED_SOURCE_SET1 | \
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BOARD_DEEP_SLEEP_DISABLED | \
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BOARD_DETECT_AP_WITH_UART | \
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BOARD_NEEDS_SYS_RST_PULL_UP | \
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BOARD_NO_INA_SUPPORT | \
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BOARD_SLAVE_CONFIG_I2C | \
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BOARD_SLAVE_CONFIG_SPI | \
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BOARD_USE_PLT_RESET | \
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BOARD_WP_DISABLE_DELAY)
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#endif /* ! __EC_BOARD_CR50_SCRATCH_REG1_H */
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