561 lines
15 KiB
C
561 lines
15 KiB
C
/* Copyright 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* X86 chipset power control module for Chrome EC */
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#include "battery.h"
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#include "charge_state.h"
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#include "chipset.h"
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#include "common.h"
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#include "console.h"
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#include "extpower.h"
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#include "i2c.h"
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#include "lb_common.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "lid_switch.h"
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#include "power.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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#include "wireless.h"
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/* Console output macros */
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#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
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#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
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/* Input state flags */
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#define IN_PGOOD_PP1050 POWER_SIGNAL_MASK(X86_PGOOD_PP1050)
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#define IN_PGOOD_PP1200 POWER_SIGNAL_MASK(X86_PGOOD_PP1200)
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#define IN_PGOOD_PP1800 POWER_SIGNAL_MASK(X86_PGOOD_PP1800)
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#define IN_PGOOD_VCORE POWER_SIGNAL_MASK(X86_PGOOD_VCORE)
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#define IN_PCH_SLP_S0_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S0_DEASSERTED)
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#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
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#define IN_PCH_SLP_S5_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S5_DEASSERTED)
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#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
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/* All non-core power rails */
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#define IN_PGOOD_ALL_NONCORE (IN_PGOOD_PP1050)
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/* All core power rails */
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#define IN_PGOOD_ALL_CORE (IN_PGOOD_VCORE)
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/* Rails required for S3 */
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#define IN_PGOOD_S3 (IN_PGOOD_PP1200)
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/* Rails required for S0 */
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#define IN_PGOOD_S0 (IN_PGOOD_ALL_NONCORE)
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/* Rails used to detect if PP5000 is up. 1.8V PGOOD is not
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* a reliable signal to use here with an internal pullup. */
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#define IN_PGOOD_PP5000 (IN_PGOOD_PP1050 | IN_PGOOD_PP1200)
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/* All PM_SLP signals from PCH deasserted */
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#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
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IN_PCH_SLP_S5_DEASSERTED | \
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IN_PCH_SLP_SUS_DEASSERTED)
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/* All inputs in the right state for S0 */
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#define IN_ALL_S0 (IN_PGOOD_ALL_NONCORE | IN_PGOOD_ALL_CORE | \
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IN_ALL_PM_SLP_DEASSERTED)
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static int throttle_cpu; /* Throttle CPU? */
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static uint32_t pp5000_in_g3; /* Turn PP5000 on in G3? */
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void chipset_force_shutdown(enum chipset_shutdown_reason reason)
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{
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CPRINTS("%s(%d)", __func__, reason);
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report_ap_reset(reason);
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/*
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* Force off. This condition will reset once the state machine
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* transitions to G3.
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*/
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gpio_set_level(GPIO_PCH_DPWROK, 0);
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gpio_set_level(GPIO_PCH_RSMRST_L, 0);
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}
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static void chipset_force_g3(void)
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{
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CPRINTS("Forcing G3");
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gpio_disable_interrupt(GPIO_VCORE_PGOOD);
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gpio_set_level(GPIO_PCH_PWROK, 0);
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gpio_set_level(GPIO_SYS_PWROK, 0);
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gpio_set_level(GPIO_PP1050_EN, 0);
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gpio_set_level(GPIO_PP1200_EN, 0);
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gpio_set_level(GPIO_PP1800_EN, 0);
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gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
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gpio_set_level(GPIO_PP5000_USB_EN, 0);
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/* Disable PP5000 if allowed */
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if (!pp5000_in_g3)
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gpio_set_level(GPIO_PP5000_EN, 0);
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gpio_set_level(GPIO_PCH_RSMRST_L, 0);
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gpio_set_level(GPIO_PCH_DPWROK, 0);
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gpio_set_level(GPIO_PP3300_DSW_EN, 0);
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wireless_set_state(WIRELESS_OFF);
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}
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static void chipset_reset_rtc(void)
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{
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/*
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* Assert RTCRST# to the PCH long enough for it to latch the
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* assertion and reset the internal RTC backed state.
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*/
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CPRINTS("Asserting RTCRST# to PCH");
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gpio_set_level(GPIO_PCH_RTCRST_L, 0);
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udelay(100);
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gpio_set_level(GPIO_PCH_RTCRST_L, 1);
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udelay(10 * MSEC);
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}
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void chipset_reset(enum chipset_reset_reason reason)
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{
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CPRINTS("%s(%d)", __func__, reason);
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report_ap_reset(reason);
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/*
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* Send a RCIN# pulse to the PCH. This just causes it to
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* assert INIT# to the CPU without dropping power or asserting
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* PLTRST# to reset the rest of the system.
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*/
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/*
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* Pulse must be at least 16 PCI clocks long = 500 ns.
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*/
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gpio_set_level(GPIO_PCH_RCIN_L, 0);
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udelay(10);
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gpio_set_level(GPIO_PCH_RCIN_L, 1);
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}
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void chipset_throttle_cpu(int throttle)
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{
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if (chipset_in_state(CHIPSET_STATE_ON))
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gpio_set_level(GPIO_CPU_PROCHOT, throttle);
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}
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enum power_state power_chipset_init(void)
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{
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/*
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* If we're switching between images without rebooting, see if the x86
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* is already powered on; if so, leave it there instead of cycling
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* through G3.
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*/
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if (system_jumped_to_this_image()) {
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if ((power_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
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/* Disable idle task deep sleep when in S0. */
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disable_sleep(SLEEP_MASK_AP_RUN);
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CPRINTS("already in S0");
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return POWER_S0;
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} else {
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/* Force all signals to their G3 states */
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chipset_force_g3();
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}
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}
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return POWER_G3;
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}
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enum power_state power_handle_state(enum power_state state)
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{
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struct batt_params batt;
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switch (state) {
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case POWER_G3:
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break;
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case POWER_S5:
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while ((power_get_signals() & IN_PCH_SLP_S5_DEASSERTED) == 0) {
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if (task_wait_event(SECOND*4) == TASK_EVENT_TIMER) {
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CPRINTS("timeout waiting for S5 exit");
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/* Put system in G3 and assert RTCRST# */
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chipset_force_g3();
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chipset_reset_rtc();
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/* Try to power back up after RTC reset */
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return POWER_G3S5;
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}
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}
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return POWER_S5S3; /* Power up to next state */
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break;
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case POWER_S3:
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/* Check for state transitions */
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if (!power_has_signals(IN_PGOOD_S3)) {
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/* Required rail went away */
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chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
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return POWER_S3S5;
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} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
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/* Power up to next state */
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return POWER_S3S0;
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} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0) {
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/* Power down to next state */
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return POWER_S3S5;
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}
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break;
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case POWER_S0:
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if (!power_has_signals(IN_PGOOD_S0)) {
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/* Required rail went away */
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chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
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return POWER_S0S3;
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} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
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/* Power down to next state */
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return POWER_S0S3;
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}
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break;
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case POWER_G3S5:
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/* Return to G3 if battery level is too low */
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if (charge_want_shutdown() ||
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charge_prevent_power_on(0)) {
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CPRINTS("power-up inhibited");
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chipset_force_g3();
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return POWER_G3;
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}
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/* Enable 3.3V DSW */
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gpio_set_level(GPIO_PP3300_DSW_EN, 1);
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/*
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* Wait 10ms after +3VALW good, since that powers VccDSW and
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* VccSUS.
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*/
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msleep(10);
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/* Enable PP5000 (5V) rail as 1.05V and 1.2V rails need 5V
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* rail to regulate properly. */
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gpio_set_level(GPIO_PP5000_EN, 1);
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/* Wait for PP1050/PP1200 PGOOD to go LOW to
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* indicate that PP5000 is stable */
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while ((power_get_signals() & IN_PGOOD_PP5000) != 0) {
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if (task_wait_event(SECOND) == TASK_EVENT_TIMER) {
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CPRINTS("timeout waiting for PP5000");
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chipset_force_g3();
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return POWER_G3;
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}
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}
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/*
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* TODO(crosbug.com/p/31583): Temporary hack to allow booting
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* without battery. If battery is not present here, then delay
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* to give time for PD MCU to negotiate to 20V.
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*/
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battery_get_params(&batt);
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if (batt.is_present != BP_YES && !system_is_locked()) {
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CPRINTS("Attempting boot w/o battery, adding delay");
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msleep(500);
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}
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/* Assert DPWROK */
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gpio_set_level(GPIO_PCH_DPWROK, 1);
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/*
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* Wait for SLP_SUS before enabling 1.05V rail.
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*/
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if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) {
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CPRINTS("timeout waiting for SLP_SUS deassert");
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chipset_force_g3();
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return POWER_G3;
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}
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/* Enable PP1050 rail. */
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gpio_set_level(GPIO_PP1050_EN, 1);
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/* Wait for 1.05V to come up and CPU to notice */
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if (power_wait_signals(IN_PGOOD_PP1050)) {
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CPRINTS("timeout waiting for PP1050");
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chipset_force_g3();
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return POWER_G3;
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}
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/* Add 10ms delay between SUSP_VR and RSMRST */
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msleep(10);
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/* Deassert RSMRST# */
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gpio_set_level(GPIO_PCH_RSMRST_L, 1);
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/* Wait 5ms for SUSCLK to stabilize */
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msleep(5);
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/* Call hook to indicate out of G3 state */
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hook_notify(HOOK_CHIPSET_PRE_INIT);
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return POWER_S5;
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case POWER_S5S3:
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/* Turn on power to RAM */
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gpio_set_level(GPIO_PP1800_EN, 1);
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gpio_set_level(GPIO_PP1200_EN, 1);
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if (power_wait_signals(IN_PGOOD_S3)) {
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gpio_set_level(GPIO_PP1800_EN, 0);
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gpio_set_level(GPIO_PP1200_EN, 0);
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chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
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return POWER_S5;
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}
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/*
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* Take lightbar out of reset, now that +5VALW is
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* available and we won't leak +3VALW through the reset
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* line.
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*/
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i2c_lock(I2C_PORT_LIGHTBAR, 1);
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gpio_set_level(GPIO_LIGHTBAR_RESET_L, 1);
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msleep(1);
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lb_init(0);
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msleep(100);
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i2c_lock(I2C_PORT_LIGHTBAR, 0);
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/*
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* Enable touchpad power so it can wake the system from
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* suspend.
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*/
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gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
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/* Turn on USB power rail. */
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gpio_set_level(GPIO_PP5000_USB_EN, 1);
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/* Call hooks now that rails are up */
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hook_notify(HOOK_CHIPSET_STARTUP);
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return POWER_S3;
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case POWER_S3S0:
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/* Turn on 3.3V DSW gated rail for core regulator */
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gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 1);
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/* Wait 20ms before allowing VCCST_PGOOD to rise. */
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msleep(20);
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/* Enable wireless. */
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wireless_set_state(WIRELESS_ON);
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/* Make sure the touchscreen is on, too. */
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gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 1);
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/* Wait for non-core power rails good */
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if (power_wait_signals(IN_PGOOD_S0)) {
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gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
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wireless_set_state(WIRELESS_OFF);
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gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 1);
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chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
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return POWER_S3;
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}
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/* Call hooks now that rails are up */
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hook_notify(HOOK_CHIPSET_RESUME);
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/*
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* Disable idle task deep sleep. This means that the low
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* power idle task will not go into deep sleep while in S0.
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*/
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disable_sleep(SLEEP_MASK_AP_RUN);
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/*
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* Throttle CPU if necessary. This should only be asserted
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* when +VCCP is powered (it is by now).
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*/
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gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
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/*
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* VCORE_PGOOD signal buffer is powered by PP1050_VCCST which
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* is gated by SLP_S3 assertion. Now the signal is valid and
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* can be enabled as an interrupt source.
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*/
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gpio_enable_interrupt(GPIO_VCORE_PGOOD);
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/* Set PCH_PWROK */
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gpio_set_level(GPIO_PCH_PWROK, 1);
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/* Wait for VCORE_PGOOD before enabling SYS_PWROK */
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if (power_wait_signals(IN_PGOOD_VCORE)) {
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gpio_disable_interrupt(GPIO_VCORE_PGOOD);
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hook_notify(HOOK_CHIPSET_SUSPEND);
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enable_sleep(SLEEP_MASK_AP_RUN);
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gpio_set_level(GPIO_PCH_PWROK, 0);
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gpio_set_level(GPIO_CPU_PROCHOT, 0);
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gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
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gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 1);
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wireless_set_state(WIRELESS_OFF);
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chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
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return POWER_S3;
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}
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/*
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* Wait a bit for all voltages to be good. PCIe devices need
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* 99ms, but mini-PCIe devices only need 1ms. Intel recommends
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* at least 5ms between ALL_SYS_PWRGD and SYS_PWROK.
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*/
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msleep(5);
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/* Set SYS_PWROK */
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gpio_set_level(GPIO_SYS_PWROK, 1);
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return POWER_S0;
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case POWER_S0S3:
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/* Call hooks before we remove power rails */
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hook_notify(HOOK_CHIPSET_SUSPEND);
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/* Clear PCH_PWROK */
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gpio_set_level(GPIO_SYS_PWROK, 0);
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gpio_set_level(GPIO_PCH_PWROK, 0);
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/* Wait 40ns */
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udelay(1);
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/* Suspend wireless */
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wireless_set_state(WIRELESS_SUSPEND);
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/*
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* Enable idle task deep sleep. Allow the low power idle task
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* to go into deep sleep in S3 or lower.
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*/
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enable_sleep(SLEEP_MASK_AP_RUN);
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/* Put touchscreen in reset */
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gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
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/*
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* Deassert prochot since CPU is off and we're about to drop
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* +VCCP.
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*/
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gpio_set_level(GPIO_CPU_PROCHOT, 0);
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/* Turn off DSW gated */
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gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
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/*
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* VCORE_PGOOD signal buffer is powered by PP1050_VCCST which
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* is gated by SLP_S3 assertion. The signal is no longer
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* valid and should be disabled as an interrupt source.
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*/
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gpio_disable_interrupt(GPIO_VCORE_PGOOD);
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return POWER_S3;
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case POWER_S3S5:
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/* Call hooks before we remove power rails */
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hook_notify(HOOK_CHIPSET_SHUTDOWN);
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/* Disable wireless */
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wireless_set_state(WIRELESS_OFF);
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/* Disable peripheral power */
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gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
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gpio_set_level(GPIO_PP5000_USB_EN, 0);
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/* Turn off power to RAM */
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gpio_set_level(GPIO_PP1800_EN, 0);
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gpio_set_level(GPIO_PP1200_EN, 0);
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/*
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* Put touchscreen and lightbar in reset, so we won't
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* leak +3VALW through the reset line to chips powered
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* by +5VALW.
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*
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* (Note that we're no longer powering down +5VALW due
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* to crosbug.com/p/16600, but to minimize side effects
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* of that change we'll still reset these components in
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* S5.)
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*/
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gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
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gpio_set_level(GPIO_LIGHTBAR_RESET_L, 0);
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return power_get_pause_in_s5() ? POWER_S5 : POWER_S5G3;
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case POWER_S5G3:
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/* Deassert DPWROK */
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gpio_set_level(GPIO_PCH_DPWROK, 0);
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/* Assert RSMRST# */
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gpio_set_level(GPIO_PCH_RSMRST_L, 0);
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/* Turn off power rails enabled in S5 */
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gpio_set_level(GPIO_PP1050_EN, 0);
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/* Check if we can disable PP5000 */
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|
if (!pp5000_in_g3)
|
|
gpio_set_level(GPIO_PP5000_EN, 0);
|
|
|
|
/* Disable 3.3V DSW */
|
|
gpio_set_level(GPIO_PP3300_DSW_EN, 0);
|
|
return POWER_G3;
|
|
}
|
|
|
|
return state;
|
|
}
|
|
|
|
/**
|
|
* Set PP5000 rail in G3. The mask represents the reason for
|
|
* turning on/off the PP5000 rail in G3, and enable either
|
|
* enables or disables that mask. If any bit is enabled, then
|
|
* the PP5000 rail will remain on. If all bits are cleared,
|
|
* the rail will turn off.
|
|
*
|
|
* @param mask Mask to modify
|
|
* @param enable Enable flag
|
|
*/
|
|
void set_pp5000_in_g3(int mask, int enable)
|
|
{
|
|
if (enable)
|
|
atomic_or(&pp5000_in_g3, mask);
|
|
else
|
|
atomic_clear(&pp5000_in_g3, mask);
|
|
|
|
/* if we are in G3 now, then set the rail accordingly */
|
|
if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
|
|
gpio_set_level(GPIO_PP5000_EN, !!pp5000_in_g3);
|
|
}
|
|
|
|
#ifdef CONFIG_LIGHTBAR_POWER_RAILS
|
|
/* Returns true if a change was made, NOT the new state */
|
|
int lb_power(int enabled)
|
|
{
|
|
int ret = 0;
|
|
int pp5000_en = gpio_get_level(GPIO_PP5000_EN);
|
|
|
|
set_pp5000_in_g3(PP5000_IN_G3_LIGHTBAR, enabled);
|
|
|
|
/* If the AP is on, we don't change the rails. */
|
|
if (!chipset_in_state(CHIPSET_STATE_ANY_OFF))
|
|
return ret;
|
|
|
|
/* Check if PP5000 rail changed */
|
|
if (gpio_get_level(GPIO_PP5000_EN) != pp5000_en)
|
|
ret = 1;
|
|
|
|
/*
|
|
* When turning on, we have to wait for the rails to come up
|
|
* fully before we the lightbar ICs will respond. There's not
|
|
* a reliable PGOOD signal for that (I tried), so we just
|
|
* have to wait. These delays seem to work.
|
|
*
|
|
* Note, we should delay even if the PP5000 rail was already
|
|
* enabled because we can't be sure it's been enabled long
|
|
* enough for lightbar IC to respond.
|
|
*
|
|
* Also, the lightbar do not expect other i2c traffic while
|
|
* being power up. Put a lock on the i2c bus.
|
|
* see chrome-os-partner:45223.
|
|
*/
|
|
if (enabled) {
|
|
i2c_lock(I2C_PORT_LIGHTBAR, 1);
|
|
msleep(10);
|
|
}
|
|
|
|
if (enabled != gpio_get_level(GPIO_LIGHTBAR_RESET_L)) {
|
|
ret = 1;
|
|
gpio_set_level(GPIO_LIGHTBAR_RESET_L, enabled);
|
|
msleep(1);
|
|
}
|
|
if (enabled) {
|
|
lb_init(0);
|
|
msleep(100);
|
|
i2c_lock(I2C_PORT_LIGHTBAR, 0);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#endif
|