131 lines
3.6 KiB
C
131 lines
3.6 KiB
C
/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/*
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* Tiny charger configuration. This config is used for multiple boards
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* including zinger and minimuffin.
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*/
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#ifndef __CROS_EC_BOARD_H
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#define __CROS_EC_BOARD_H
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/* 48 MHz SYSCLK clock frequency */
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#define CPU_CLOCK 48000000
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/* the UART console is on USART1 (PA9/PA10) */
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#define CONFIG_UART_CONSOLE 1
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#ifdef BOARD_ZINGER
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#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR USB_PD_HW_DEV_ID_ZINGER
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#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR 1
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#elif defined(BOARD_MINIMUFFIN)
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#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR USB_PD_HW_DEV_ID_MINIMUFFIN
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#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR 0
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#else
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#error "Board does not have a USB-PD HW Device ID"
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#endif
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/* Optional features */
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#undef CONFIG_COMMON_GPIO
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#undef CONFIG_COMMON_PANIC_OUTPUT
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#undef CONFIG_COMMON_RUNTIME
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#undef CONFIG_COMMON_TIMER
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#define CONFIG_LOW_POWER_IDLE
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#undef CONFIG_CONSOLE_CMDHELP
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#undef CONFIG_DEBUG_ASSERT
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#undef CONFIG_DEBUG_EXCEPTIONS
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#undef CONFIG_DEBUG_STACK_OVERFLOW
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#undef CONFIG_FLASH
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#undef CONFIG_FLASH_PHYSICAL
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#undef CONFIG_FMAP
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/* Not using pstate but keep some space for the public key */
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#undef CONFIG_FW_PSTATE_SIZE
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#define CONFIG_FW_PSTATE_SIZE 544
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#define CONFIG_HIBERNATE
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#define CONFIG_HIBERNATE_WAKEUP_PINS STM32_PWR_CSR_EWUP1
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#define CONFIG_HW_CRC
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#undef CONFIG_LID_SWITCH
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#define CONFIG_LTO
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#define CONFIG_RSA
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#define CONFIG_RWSIG_TYPE_USBPD1
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#define CONFIG_SHA256
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#undef CONFIG_TASK_PROFILING
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#define CONFIG_USB_POWER_DELIVERY
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#define CONFIG_USB_PD_ALT_MODE
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#undef CONFIG_USB_PD_DUAL_ROLE
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#undef CONFIG_USB_PD_INTERNAL_COMP
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#define CONFIG_USB_PD_LOGGING
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#undef CONFIG_EVENT_LOG_SIZE
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#define CONFIG_EVENT_LOG_SIZE 256
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#define CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED
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#define CONFIG_USB_PD_PORT_COUNT 1
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#define CONFIG_USB_PD_TCPC
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#define CONFIG_USB_PD_TCPM_STUB
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#undef CONFIG_USB_PD_RX_COMP_IRQ
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#define CONFIG_USB_PD_SIMPLE_DFP
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#define CONFIG_USB_PD_VBUS_DETECT_GPIO
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#define CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP
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#undef CONFIG_WATCHDOG_HELP
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#undef CONFIG_WATCHDOG_PERIOD_MS
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#define CONFIG_WATCHDOG_PERIOD_MS 2300
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/* debug printf flash footprinf is about 1400 bytes */
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#define CONFIG_DEBUG_PRINTF
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#define UARTN CONFIG_UART_CONSOLE
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#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
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/* USB configuration */
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#if defined(BOARD_ZINGER)
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#define CONFIG_USB_PID 0x5012
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#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
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#elif defined(BOARD_MINIMUFFIN)
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#define CONFIG_USB_PID 0x5013
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#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
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#endif
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#ifndef __ASSEMBLER__
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#include "common.h"
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/* No GPIO abstraction layer */
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enum gpio_signal;
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enum adc_channel {
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ADC_CH_CC1_PD = 1,
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ADC_CH_A_SENSE = 2,
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ADC_CH_V_SENSE = 3,
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/* Number of ADC channels */
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ADC_CH_COUNT
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};
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/* captive cable : no CC2 */
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#define ADC_CH_CC2_PD ADC_CH_CC1_PD
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/* 3.0A Rp */
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#define PD_SRC_VNC (PD_SRC_3_0_VNC_MV * 4096 / 3300/* 12-bit ADC, 3.3V range */)
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/* delay necessary for the voltage transition on the power supply */
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#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */
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#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
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/* Initialize all useful registers */
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void hardware_init(void);
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/* last interrupt event */
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extern volatile uint32_t last_event;
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/* RW section flashing */
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int flash_erase_rw(void);
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int flash_write_rw(int offset, int size, const char *data);
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void flash_physical_permanent_protect(void);
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int flash_physical_is_permanently_protected(void);
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uint8_t *flash_hash_rw(void);
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int is_ro_mode(void);
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void __enter_hibernate(uint32_t seconds, uint32_t microseconds);
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#endif /* !__ASSEMBLER__ */
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#endif /* __CROS_EC_BOARD_H */
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