163 lines
5.8 KiB
C
163 lines
5.8 KiB
C
/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_CHIP_H
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#define __CROS_EC_CONFIG_CHIP_H
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#if defined(BOARD)
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#include "core/cortex-m/config_core.h"
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#include "hw_regdefs.h"
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#endif
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/* Describe the RAM layout */
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#define CONFIG_RAM_BASE 0x10000
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#define CONFIG_RAM_SIZE 0x10000
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/* Flash chip specifics */
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#define CONFIG_FLASH_BANK_SIZE 0x800 /* protect bank size */
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#define CONFIG_FLASH_ERASE_SIZE 0x800 /* erase bank size */
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/* This flash can only be written as 4-byte words (aligned properly, too). */
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#define CONFIG_FLASH_WRITE_SIZE 4 /* min write size (bytes) */
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/* But we have a 32-word buffer for writing multiple adjacent cells */
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#define CONFIG_FLASH_WRITE_IDEAL_SIZE 128 /* best write size (bytes) */
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/* The flash controller prevents bulk writes that cross row boundaries */
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#define CONFIG_FLASH_ROW_SIZE 256 /* row size */
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/* Describe the flash layout */
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#define CONFIG_PROGRAM_MEMORY_BASE 0x40000
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#define CONFIG_FLASH_SIZE (512 * 1024)
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#define CONFIG_FLASH_ERASED_VALUE32 (-1U)
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#undef CONFIG_RO_HEAD_ROOM
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#define CONFIG_RO_HEAD_ROOM 1024 /* Room for ROM signature. */
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#undef CONFIG_RW_HEAD_ROOM
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#define CONFIG_RW_HEAD_ROOM CONFIG_RO_HEAD_ROOM /* same for RW */
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/* Memory-mapped internal flash */
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#define CONFIG_INTERNAL_STORAGE
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#define CONFIG_MAPPED_STORAGE
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/* Program is run directly from storage */
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#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
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/* Interval between HOOK_TICK notifications */
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#define HOOK_TICK_INTERVAL_MS 500
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#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
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/* System stack size */
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#define CONFIG_STACK_SIZE 1024
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/* Idle task stack size */
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#define IDLE_TASK_STACK_SIZE 512
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/* Default task stack size */
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#define TASK_STACK_SIZE 488
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/* Larger task stack size, for hook task */
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#define LARGER_TASK_STACK_SIZE 640
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/* Magic for gpio.inc */
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#define GPIO_PIN(port, index) (port), (1 << (index))
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#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
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#define DUMMY_GPIO_BANK 0
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#define PCLK_FREQ (24 * 1000 * 1000)
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/* Number of IRQ vectors on the NVIC */
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#define CONFIG_IRQ_COUNT (GC_INTERRUPTS_COUNT - 15)
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/* We'll have some special commands of our own */
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#define CONFIG_EXTENSION_COMMAND 0xbaccd00a
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/* Chip needs to do custom pre-init */
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#define CONFIG_CHIP_PRE_INIT
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/*
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* The flash memory is implemented in two halves. The SoC bootrom will look for
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* the first-stage bootloader at the beginning of each of the two halves and
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* prefer the newer one if both are valid. In EC terminology the bootloader
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* would be called the RO firmware, so we actually have two, not one. The
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* bootloader also looks in each half of the flash for a valid RW firmware, so
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* we have two possible RW images as well. The RO and RW images are not tightly
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* coupled, so either RO image can choose to boot either RW image.
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*
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* The EC firmware configuration is not (yet?) prepared to handle multiple,
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* non-contiguous, RO/RW combinations, so there's a bit of hackery to make this
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* work.
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*
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* The following macros try to make this all work.
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*/
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/* This isn't optional, since the bootrom will always look for both */
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#define CHIP_HAS_RO_B
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/* It's easier for us to consider each half as having its own RO and RW */
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#define CFG_FLASH_HALF (CONFIG_FLASH_SIZE >> 1)
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/*
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* We'll reserve some space at the top of each flash half for persistent
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* storage and other stuff that's not part of the RW image. We don't promise to
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* use these two areas for the same thing, it's just more convenient to make
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* them the same size.
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*/
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#define CFG_TOP_SIZE 0x3800
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#define CFG_TOP_A_OFF (CFG_FLASH_HALF - CFG_TOP_SIZE)
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#define CFG_TOP_B_OFF (CONFIG_FLASH_SIZE - CFG_TOP_SIZE)
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/* The RO images start at the very beginning of each flash half */
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#define CONFIG_RO_MEM_OFF 0
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#define CHIP_RO_B_MEM_OFF CFG_FLASH_HALF
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/* Size reserved for each RO image */
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#define CONFIG_RO_SIZE 0x4000
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/*
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* RW images start right after the reserved-for-RO areas in each half, but only
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* because that's where the RO images look for them. It's not a HW constraint.
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*/
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#define CONFIG_RW_MEM_OFF CONFIG_RO_SIZE
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#define CONFIG_RW_B_MEM_OFF (CFG_FLASH_HALF + CONFIG_RW_MEM_OFF)
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/* Size reserved for each RW image */
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#define CONFIG_RW_SIZE (CFG_FLASH_HALF - CONFIG_RW_MEM_OFF - CFG_TOP_SIZE)
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/*
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* These are needed in a couple of places, but aren't very meaningful. Because
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* we have two RO and two RW images, these values don't really match what's
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* described in the EC Image Geometry Spec at www.chromium.org.
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*/
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/* TODO(wfrichar): Make them meaningful or learn to do without */
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#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_FLASH_SIZE
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#define CONFIG_EC_WRITABLE_STORAGE_OFF 0
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_FLASH_SIZE
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#define CONFIG_RO_STORAGE_OFF 0
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#define CONFIG_RW_STORAGE_OFF 0
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#define CONFIG_WP_STORAGE_OFF 0
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#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
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/*
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* Note: early versions of the SoC would let us build and manually sign our own
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* bootloaders, and the RW images could be self-signed. Production SoCs require
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* officially-signed binary blobs to use for the RO bootloader(s), and the RW
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* images that we build must be manually signed. So even though we generate RO
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* firmware images, they may not be useful.
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*/
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#define CONFIG_CUSTOMIZED_RO
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/* Number of I2C ports */
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#define I2C_PORT_COUNT 2
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#define CONFIG_FLASH_LOG_SPACE CONFIG_FLASH_BANK_SIZE
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/*
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* Flash log occupies space in the top of RO_B section, its counterpart in
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* RO_A is occupied by the certs.
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*/
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#define CONFIG_FLASH_LOG_BASE \
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(CONFIG_PROGRAM_MEMORY_BASE + CHIP_RO_B_MEM_OFF + CONFIG_RO_SIZE - \
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CONFIG_FLASH_LOG_SPACE)
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#endif /* __CROS_EC_CONFIG_CHIP_H */
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