280 lines
14 KiB
C
280 lines
14 KiB
C
/* Copyright 2019 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* MAX32660 Registers, Bit Masks and Bit Positions for the TMR Peripheral */
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#ifndef _TMR_REGS_H_
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#define _TMR_REGS_H_
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/* **** Includes **** */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/* **** Definitions **** */
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/**
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* 32-bit reloadable timer that can be used for timing and event
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* counting.
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*/
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/**
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* Structure type to access the TMR Registers.
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*/
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typedef struct {
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__IO uint32_t cnt; /**< <tt>\b 0x00:<\tt> TMR CNT Register */
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__IO uint32_t cmp; /**< <tt>\b 0x04:<\tt> TMR CMP Register */
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__IO uint32_t pwm; /**< <tt>\b 0x08:<\tt> TMR PWM Register */
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__IO uint32_t intr; /**< <tt>\b 0x0C:<\tt> TMR INTR Register */
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__IO uint32_t cn; /**< <tt>\b 0x10:<\tt> TMR CN Register */
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__IO uint32_t nolcmp; /**< <tt>\b 0x14:<\tt> TMR NOLCMP Register */
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} mxc_tmr_regs_t;
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/**
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* TMR Peripheral Register Offsets from the TMR Base Peripheral
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* Address.
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*/
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#define MXC_R_TMR_CNT \
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((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> \
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0x0x000 */
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#define MXC_R_TMR_CMP \
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((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> \
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0x0x004 */
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#define MXC_R_TMR_PWM \
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((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> \
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0x0x008 */
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#define MXC_R_TMR_INTR \
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((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> \
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0x0x00C */
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#define MXC_R_TMR_CN \
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((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> \
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0x0x010 */
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#define MXC_R_TMR_NOLCMP \
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((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> \
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0x0x014 */
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/**
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* Clear Interrupt. Writing a value (0 or 1) to a bit in this register
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* clears the associated interrupt.
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*/
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#define MXC_F_TMR_INTR_IRQ_CLR_POS 0 /**< INTR_IRQ_CLR Position */
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#define MXC_F_TMR_INTR_IRQ_CLR \
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((uint32_t)(0x1UL \
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<< MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */
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/**
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* Timer Control Register.
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*/
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#define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */
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#define MXC_F_TMR_CN_TMODE \
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((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */
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#define MXC_V_TMR_CN_TMODE_ONESHOT \
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((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */
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#define MXC_S_TMR_CN_TMODE_ONESHOT \
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(MXC_V_TMR_CN_TMODE_ONESHOT \
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<< MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */
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#define MXC_V_TMR_CN_TMODE_CONTINUOUS \
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((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */
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#define MXC_S_TMR_CN_TMODE_CONTINUOUS \
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(MXC_V_TMR_CN_TMODE_CONTINUOUS \
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<< MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */
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#define MXC_V_TMR_CN_TMODE_COUNTER \
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((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */
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#define MXC_S_TMR_CN_TMODE_COUNTER \
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(MXC_V_TMR_CN_TMODE_COUNTER \
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<< MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */
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#define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */
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#define MXC_S_TMR_CN_TMODE_PWM \
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(MXC_V_TMR_CN_TMODE_PWM \
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<< MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */
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#define MXC_V_TMR_CN_TMODE_CAPTURE \
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((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */
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#define MXC_S_TMR_CN_TMODE_CAPTURE \
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(MXC_V_TMR_CN_TMODE_CAPTURE \
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<< MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */
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#define MXC_V_TMR_CN_TMODE_COMPARE \
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((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */
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#define MXC_S_TMR_CN_TMODE_COMPARE \
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(MXC_V_TMR_CN_TMODE_COMPARE \
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<< MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */
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#define MXC_V_TMR_CN_TMODE_GATED \
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((uint32_t)0x6UL) /**< CN_TMODE_GATED Value \
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*/
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#define MXC_S_TMR_CN_TMODE_GATED \
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(MXC_V_TMR_CN_TMODE_GATED \
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<< MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
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#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \
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((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */
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#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE \
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(MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \
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<< MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */
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#define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */
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#define MXC_F_TMR_CN_PRES \
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((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */
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#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */
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#define MXC_S_TMR_CN_PRES_DIV1 \
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(MXC_V_TMR_CN_PRES_DIV1 \
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<< MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */
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#define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */
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#define MXC_S_TMR_CN_PRES_DIV2 \
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(MXC_V_TMR_CN_PRES_DIV2 \
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<< MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */
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#define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */
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#define MXC_S_TMR_CN_PRES_DIV4 \
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(MXC_V_TMR_CN_PRES_DIV4 \
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<< MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */
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#define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */
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#define MXC_S_TMR_CN_PRES_DIV8 \
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(MXC_V_TMR_CN_PRES_DIV8 \
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<< MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */
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#define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */
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#define MXC_S_TMR_CN_PRES_DIV16 \
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(MXC_V_TMR_CN_PRES_DIV16 \
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<< MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */
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#define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */
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#define MXC_S_TMR_CN_PRES_DIV32 \
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(MXC_V_TMR_CN_PRES_DIV32 \
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<< MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */
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#define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */
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#define MXC_S_TMR_CN_PRES_DIV64 \
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(MXC_V_TMR_CN_PRES_DIV64 \
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<< MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */
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#define MXC_V_TMR_CN_PRES_DIV128 \
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((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value \
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*/
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#define MXC_S_TMR_CN_PRES_DIV128 \
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(MXC_V_TMR_CN_PRES_DIV128 \
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<< MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */
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#define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */
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#define MXC_F_TMR_CN_TPOL \
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((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */
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#define MXC_V_TMR_CN_TPOL_ACTIVEHI \
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((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */
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#define MXC_S_TMR_CN_TPOL_ACTIVEHI \
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(MXC_V_TMR_CN_TPOL_ACTIVEHI \
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<< MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */
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#define MXC_V_TMR_CN_TPOL_ACTIVELO \
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((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */
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#define MXC_S_TMR_CN_TPOL_ACTIVELO \
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(MXC_V_TMR_CN_TPOL_ACTIVELO \
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<< MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */
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#define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */
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#define MXC_F_TMR_CN_TEN \
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((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */
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#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */
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#define MXC_S_TMR_CN_TEN_DIS \
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(MXC_V_TMR_CN_TEN_DIS \
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<< MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting */
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#define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */
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#define MXC_S_TMR_CN_TEN_EN \
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(MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting \
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*/
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#define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */
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#define MXC_F_TMR_CN_PRES3 \
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((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */
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#define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */
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#define MXC_F_TMR_CN_PWMSYNC \
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((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask \
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*/
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#define MXC_V_TMR_CN_PWMSYNC_DIS \
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((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value \
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*/
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#define MXC_S_TMR_CN_PWMSYNC_DIS \
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(MXC_V_TMR_CN_PWMSYNC_DIS \
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<< MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_DIS Setting */
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#define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */
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#define MXC_S_TMR_CN_PWMSYNC_EN \
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(MXC_V_TMR_CN_PWMSYNC_EN \
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<< MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */
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#define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */
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#define MXC_F_TMR_CN_NOLHPOL \
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((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask \
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*/
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#define MXC_V_TMR_CN_NOLHPOL_DIS \
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((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value \
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*/
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#define MXC_S_TMR_CN_NOLHPOL_DIS \
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(MXC_V_TMR_CN_NOLHPOL_DIS \
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<< MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_DIS Setting */
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#define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */
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#define MXC_S_TMR_CN_NOLHPOL_EN \
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(MXC_V_TMR_CN_NOLHPOL_EN \
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<< MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */
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#define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */
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#define MXC_F_TMR_CN_NOLLPOL \
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((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask \
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*/
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#define MXC_V_TMR_CN_NOLLPOL_DIS \
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((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value \
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*/
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#define MXC_S_TMR_CN_NOLLPOL_DIS \
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(MXC_V_TMR_CN_NOLLPOL_DIS \
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<< MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_DIS Setting */
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#define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */
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#define MXC_S_TMR_CN_NOLLPOL_EN \
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(MXC_V_TMR_CN_NOLLPOL_EN \
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<< MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */
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#define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */
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#define MXC_F_TMR_CN_PWMCKBD \
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((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask \
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*/
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#define MXC_V_TMR_CN_PWMCKBD_DIS \
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((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value \
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*/
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#define MXC_S_TMR_CN_PWMCKBD_DIS \
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(MXC_V_TMR_CN_PWMCKBD_DIS \
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<< MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_DIS Setting */
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#define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */
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#define MXC_S_TMR_CN_PWMCKBD_EN \
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(MXC_V_TMR_CN_PWMCKBD_EN \
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<< MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */
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/**
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* Timer Non-Overlapping Compare Register.
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*/
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#define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */
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#define MXC_F_TMR_NOLCMP_NOLLCMP \
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((uint32_t)( \
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0xFFUL \
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<< MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */
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#define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */
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#define MXC_F_TMR_NOLCMP_NOLHCMP \
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((uint32_t)( \
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0xFFUL \
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<< MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _TMR_REGS_H_ */
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