678 lines
37 KiB
C
678 lines
37 KiB
C
/* Copyright 2019 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* MAX32660 Registers, Bit Masks and Bit Positions for the UART Peripheral */
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#ifndef _UART_REGS_H_
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#define _UART_REGS_H_
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/* **** Includes **** */
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#include <stdint.h>
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/**
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* Structure type to access the UART Registers.
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*/
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typedef struct {
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__IO uint32_t ctrl; /**< <tt>\b 0x00:<\tt> UART CTRL Register */
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__IO uint32_t
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thresh_ctrl; /**< <tt>\b 0x04:<\tt> UART THRESH_CTRL Register */
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__I uint32_t status; /**< <tt>\b 0x08:<\tt> UART STATUS Register */
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__IO uint32_t int_en; /**< <tt>\b 0x0C:<\tt> UART INT_EN Register */
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__IO uint32_t int_fl; /**< <tt>\b 0x10:<\tt> UART INT_FL Register */
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__IO uint32_t baud0; /**< <tt>\b 0x14:<\tt> UART BAUD0 Register */
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__IO uint32_t baud1; /**< <tt>\b 0x18:<\tt> UART BAUD1 Register */
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__IO uint32_t fifo; /**< <tt>\b 0x1C:<\tt> UART FIFO Register */
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__IO uint32_t dma; /**< <tt>\b 0x20:<\tt> UART DMA Register */
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__IO uint32_t tx_fifo; /**< <tt>\b 0x24:<\tt> UART TX_FIFO Register */
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} mxc_uart_regs_t;
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/**
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* UART Peripheral Register Offsets from the UART Base Peripheral
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* Address.
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*/
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#define MXC_R_UART_CTRL \
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((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> \
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0x0x000 */
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#define MXC_R_UART_THRESH_CTRL \
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((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> \
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0x0x004 */
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#define MXC_R_UART_STATUS \
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((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> \
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0x0x008 */
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#define MXC_R_UART_INT_EN \
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((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> \
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0x0x00C */
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#define MXC_R_UART_INT_FL \
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((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> \
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0x0x010 */
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#define MXC_R_UART_BAUD0 \
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((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> \
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0x0x014 */
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#define MXC_R_UART_BAUD1 \
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((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> \
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0x0x018 */
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#define MXC_R_UART_FIFO \
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((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> \
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0x0x01C */
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#define MXC_R_UART_DMA \
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((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> \
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0x0x020 */
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#define MXC_R_UART_TX_FIFO \
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((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> \
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0x0x024 */
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/**
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* Control Register.
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*/
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#define MXC_F_UART_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */
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#define MXC_F_UART_CTRL_ENABLE \
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((uint32_t)( \
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0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */
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#define MXC_V_UART_CTRL_ENABLE_DIS \
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((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */
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#define MXC_S_UART_CTRL_ENABLE_DIS \
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(MXC_V_UART_CTRL_ENABLE_DIS \
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<< MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */
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#define MXC_V_UART_CTRL_ENABLE_EN \
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((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value \
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*/
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#define MXC_S_UART_CTRL_ENABLE_EN \
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(MXC_V_UART_CTRL_ENABLE_EN \
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<< MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */
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#define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */
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#define MXC_F_UART_CTRL_PARITY_EN \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */
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#define MXC_V_UART_CTRL_PARITY_EN_DIS \
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((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */
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#define MXC_S_UART_CTRL_PARITY_EN_DIS \
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(MXC_V_UART_CTRL_PARITY_EN_DIS \
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<< MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */
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#define MXC_V_UART_CTRL_PARITY_EN_EN \
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((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */
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#define MXC_S_UART_CTRL_PARITY_EN_EN \
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(MXC_V_UART_CTRL_PARITY_EN_EN \
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<< MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */
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#define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */
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#define MXC_F_UART_CTRL_PARITY \
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((uint32_t)( \
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0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */
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#define MXC_V_UART_CTRL_PARITY_EVEN \
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((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */
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#define MXC_S_UART_CTRL_PARITY_EVEN \
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(MXC_V_UART_CTRL_PARITY_EVEN \
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<< MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */
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#define MXC_V_UART_CTRL_PARITY_ODD \
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((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */
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#define MXC_S_UART_CTRL_PARITY_ODD \
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(MXC_V_UART_CTRL_PARITY_ODD \
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<< MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */
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#define MXC_V_UART_CTRL_PARITY_MARK \
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((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */
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#define MXC_S_UART_CTRL_PARITY_MARK \
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(MXC_V_UART_CTRL_PARITY_MARK \
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<< MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */
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#define MXC_V_UART_CTRL_PARITY_SPACE \
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((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */
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#define MXC_S_UART_CTRL_PARITY_SPACE \
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(MXC_V_UART_CTRL_PARITY_SPACE \
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<< MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */
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#define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */
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#define MXC_F_UART_CTRL_PARMD \
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((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask \
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*/
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#define MXC_V_UART_CTRL_PARMD_1 ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */
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#define MXC_S_UART_CTRL_PARMD_1 \
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(MXC_V_UART_CTRL_PARMD_1 \
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<< MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_1 Setting */
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#define MXC_V_UART_CTRL_PARMD_0 ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */
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#define MXC_S_UART_CTRL_PARMD_0 \
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(MXC_V_UART_CTRL_PARMD_0 \
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<< MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */
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#define MXC_F_UART_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */
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#define MXC_F_UART_CTRL_TX_FLUSH \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */
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#define MXC_F_UART_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */
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#define MXC_F_UART_CTRL_RX_FLUSH \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */
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#define MXC_F_UART_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */
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#define MXC_F_UART_CTRL_BITACC \
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((uint32_t)( \
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0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */
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#define MXC_V_UART_CTRL_BITACC_FRAME \
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((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */
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#define MXC_S_UART_CTRL_BITACC_FRAME \
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(MXC_V_UART_CTRL_BITACC_FRAME \
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<< MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */
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#define MXC_V_UART_CTRL_BITACC_BIT \
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((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */
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#define MXC_S_UART_CTRL_BITACC_BIT \
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(MXC_V_UART_CTRL_BITACC_BIT \
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<< MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */
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#define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */
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#define MXC_F_UART_CTRL_CHAR_SIZE \
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((uint32_t)( \
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0x3UL \
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<< MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */
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#define MXC_V_UART_CTRL_CHAR_SIZE_5 \
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((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */
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#define MXC_S_UART_CTRL_CHAR_SIZE_5 \
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(MXC_V_UART_CTRL_CHAR_SIZE_5 \
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<< MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */
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#define MXC_V_UART_CTRL_CHAR_SIZE_6 \
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((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */
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#define MXC_S_UART_CTRL_CHAR_SIZE_6 \
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(MXC_V_UART_CTRL_CHAR_SIZE_6 \
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<< MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */
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#define MXC_V_UART_CTRL_CHAR_SIZE_7 \
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((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */
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#define MXC_S_UART_CTRL_CHAR_SIZE_7 \
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(MXC_V_UART_CTRL_CHAR_SIZE_7 \
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<< MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */
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#define MXC_V_UART_CTRL_CHAR_SIZE_8 \
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((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */
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#define MXC_S_UART_CTRL_CHAR_SIZE_8 \
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(MXC_V_UART_CTRL_CHAR_SIZE_8 \
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<< MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */
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#define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */
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#define MXC_F_UART_CTRL_STOPBITS \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */
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#define MXC_V_UART_CTRL_STOPBITS_1 \
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((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */
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#define MXC_S_UART_CTRL_STOPBITS_1 \
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(MXC_V_UART_CTRL_STOPBITS_1 \
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<< MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */
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#define MXC_V_UART_CTRL_STOPBITS_1_5 \
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((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */
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#define MXC_S_UART_CTRL_STOPBITS_1_5 \
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(MXC_V_UART_CTRL_STOPBITS_1_5 \
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<< MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */
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#define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */
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#define MXC_F_UART_CTRL_FLOW_CTRL \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */
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#define MXC_V_UART_CTRL_FLOW_CTRL_EN \
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((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */
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#define MXC_S_UART_CTRL_FLOW_CTRL_EN \
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(MXC_V_UART_CTRL_FLOW_CTRL_EN \
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<< MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */
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#define MXC_V_UART_CTRL_FLOW_CTRL_DIS \
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((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */
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#define MXC_S_UART_CTRL_FLOW_CTRL_DIS \
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(MXC_V_UART_CTRL_FLOW_CTRL_DIS \
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<< MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */
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#define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */
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#define MXC_F_UART_CTRL_FLOW_POL \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */
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#define MXC_V_UART_CTRL_FLOW_POL_0 \
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((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */
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#define MXC_S_UART_CTRL_FLOW_POL_0 \
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(MXC_V_UART_CTRL_FLOW_POL_0 \
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<< MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */
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#define MXC_V_UART_CTRL_FLOW_POL_1 \
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((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */
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#define MXC_S_UART_CTRL_FLOW_POL_1 \
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(MXC_V_UART_CTRL_FLOW_POL_1 \
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<< MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */
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#define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */
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#define MXC_F_UART_CTRL_NULL_MODEM \
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((uint32_t)( \
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0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM \
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Mask */
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#define MXC_V_UART_CTRL_NULL_MODEM_DIS \
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((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */
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#define MXC_S_UART_CTRL_NULL_MODEM_DIS \
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(MXC_V_UART_CTRL_NULL_MODEM_DIS \
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<< MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting \
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*/
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#define MXC_V_UART_CTRL_NULL_MODEM_EN \
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((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */
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#define MXC_S_UART_CTRL_NULL_MODEM_EN \
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(MXC_V_UART_CTRL_NULL_MODEM_EN \
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<< MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */
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#define MXC_F_UART_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */
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#define MXC_F_UART_CTRL_BREAK \
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((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask \
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*/
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#define MXC_V_UART_CTRL_BREAK_DIS \
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((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value \
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*/
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#define MXC_S_UART_CTRL_BREAK_DIS \
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(MXC_V_UART_CTRL_BREAK_DIS \
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<< MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */
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#define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */
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#define MXC_S_UART_CTRL_BREAK_EN \
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(MXC_V_UART_CTRL_BREAK_EN \
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<< MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */
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#define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */
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#define MXC_F_UART_CTRL_CLKSEL \
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((uint32_t)( \
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0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */
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#define MXC_V_UART_CTRL_CLKSEL_SYSTEM \
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((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */
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#define MXC_S_UART_CTRL_CLKSEL_SYSTEM \
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(MXC_V_UART_CTRL_CLKSEL_SYSTEM \
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<< MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */
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#define MXC_V_UART_CTRL_CLKSEL_ALTERNATE \
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((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */
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#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE \
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(MXC_V_UART_CTRL_CLKSEL_ALTERNATE \
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<< MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */
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#define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */
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#define MXC_F_UART_CTRL_RX_TO \
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((uint32_t)( \
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0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */
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/**
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* Threshold Control register.
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*/
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#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS \
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0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */
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#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH \
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((uint32_t)( \
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0x3FUL \
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<< MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**< \
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THRESH_CTRL_RX_FIFO_THRESH \
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Mask */
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#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS \
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8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */
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#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH \
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((uint32_t)( \
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0x3FUL \
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<< MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**< \
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THRESH_CTRL_TX_FIFO_THRESH \
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Mask */
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#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS \
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16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */
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#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH \
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((uint32_t)( \
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0x3FUL \
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<< MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**< \
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THRESH_CTRL_RTS_FIFO_THRESH \
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Mask */
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/**
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* Status Register.
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*/
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#define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */
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#define MXC_F_UART_STATUS_TX_BUSY \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */
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#define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */
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#define MXC_F_UART_STATUS_RX_BUSY \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */
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#define MXC_F_UART_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */
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#define MXC_F_UART_STATUS_PARITY \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */
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#define MXC_F_UART_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */
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#define MXC_F_UART_STATUS_BREAK \
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((uint32_t)(0x1UL \
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<< MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */
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#define MXC_F_UART_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */
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#define MXC_F_UART_STATUS_RX_EMPTY \
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((uint32_t)( \
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0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY \
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Mask */
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#define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */
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#define MXC_F_UART_STATUS_RX_FULL \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
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#define MXC_F_UART_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */
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#define MXC_F_UART_STATUS_TX_EMPTY \
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((uint32_t)( \
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0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY \
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Mask */
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#define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */
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#define MXC_F_UART_STATUS_TX_FULL \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
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#define MXC_F_UART_STATUS_RX_FIFO_CNT_POS \
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8 /**< STATUS_RX_FIFO_CNT Position \
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*/
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#define MXC_F_UART_STATUS_RX_FIFO_CNT \
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((uint32_t)( \
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0x3FUL \
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<< MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT \
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Mask */
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#define MXC_F_UART_STATUS_TX_FIFO_CNT_POS \
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16 /**< STATUS_TX_FIFO_CNT Position \
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*/
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#define MXC_F_UART_STATUS_TX_FIFO_CNT \
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((uint32_t)( \
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0x3FUL \
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<< MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT \
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Mask */
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#define MXC_F_UART_STATUS_RX_TO_POS 24 /**< STATUS_RX_TO Position */
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#define MXC_F_UART_STATUS_RX_TO \
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((uint32_t)(0x1UL \
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<< MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */
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/**
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* Interrupt Enable Register.
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*/
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#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS \
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0 /**< INT_EN_RX_FRAME_ERROR Position */
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#define MXC_F_UART_INT_EN_RX_FRAME_ERROR \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< \
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INT_EN_RX_FRAME_ERROR \
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Mask */
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#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS \
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1 /**< INT_EN_RX_PARITY_ERROR Position */
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#define MXC_F_UART_INT_EN_RX_PARITY_ERROR \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< \
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INT_EN_RX_PARITY_ERROR \
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Mask */
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#define MXC_F_UART_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */
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#define MXC_F_UART_INT_EN_CTS_CHANGE \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE \
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Mask */
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#define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */
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#define MXC_F_UART_INT_EN_RX_OVERRUN \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN \
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Mask */
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#define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS \
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4 /**< INT_EN_RX_FIFO_THRESH Position */
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#define MXC_F_UART_INT_EN_RX_FIFO_THRESH \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**< \
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INT_EN_RX_FIFO_THRESH \
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Mask */
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#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS \
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5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */
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#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< \
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INT_EN_TX_FIFO_ALMOST_EMPTY \
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Mask */
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#define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS \
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6 /**< INT_EN_TX_FIFO_THRESH Position */
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#define MXC_F_UART_INT_EN_TX_FIFO_THRESH \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**< \
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INT_EN_TX_FIFO_THRESH \
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Mask */
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#define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */
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#define MXC_F_UART_INT_EN_BREAK \
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((uint32_t)(0x1UL \
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<< MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */
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#define MXC_F_UART_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */
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#define MXC_F_UART_INT_EN_RX_TIMEOUT \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT \
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Mask */
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#define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */
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#define MXC_F_UART_INT_EN_LAST_BREAK \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK \
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Mask */
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/**
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* Interrupt Status Flags.
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*/
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#define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS \
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0 /**< INT_FL_RX_FRAME_ERROR Position */
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#define MXC_F_UART_INT_FL_RX_FRAME_ERROR \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**< \
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INT_FL_RX_FRAME_ERROR \
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Mask */
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#define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS \
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1 /**< INT_FL_RX_PARITY_ERROR Position */
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#define MXC_F_UART_INT_FL_RX_PARITY_ERROR \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**< \
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INT_FL_RX_PARITY_ERROR \
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Mask */
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#define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */
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#define MXC_F_UART_INT_FL_CTS_CHANGE \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE \
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Mask */
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#define MXC_F_UART_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */
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#define MXC_F_UART_INT_FL_RX_OVERRUN \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN \
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Mask */
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#define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS \
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4 /**< INT_FL_RX_FIFO_THRESH Position */
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#define MXC_F_UART_INT_FL_RX_FIFO_THRESH \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**< \
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INT_FL_RX_FIFO_THRESH \
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Mask */
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#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS \
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5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */
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#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< \
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INT_FL_TX_FIFO_ALMOST_EMPTY \
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Mask */
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#define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS \
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6 /**< INT_FL_TX_FIFO_THRESH Position */
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#define MXC_F_UART_INT_FL_TX_FIFO_THRESH \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**< \
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INT_FL_TX_FIFO_THRESH \
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Mask */
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#define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */
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#define MXC_F_UART_INT_FL_BREAK \
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((uint32_t)(0x1UL \
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<< MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */
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#define MXC_F_UART_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */
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#define MXC_F_UART_INT_FL_RX_TIMEOUT \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT \
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Mask */
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#define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */
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#define MXC_F_UART_INT_FL_LAST_BREAK \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK \
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Mask */
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/**
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* Baud rate register. Integer portion.
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*/
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#define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */
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#define MXC_F_UART_BAUD0_IBAUD \
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((uint32_t)(0xFFFUL \
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<< MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */
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#define MXC_F_UART_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */
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#define MXC_F_UART_BAUD0_FACTOR \
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((uint32_t)(0x3UL \
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<< MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */
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#define MXC_V_UART_BAUD0_FACTOR_128 \
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((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */
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#define MXC_S_UART_BAUD0_FACTOR_128 \
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(MXC_V_UART_BAUD0_FACTOR_128 \
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<< MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */
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#define MXC_V_UART_BAUD0_FACTOR_64 \
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((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */
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#define MXC_S_UART_BAUD0_FACTOR_64 \
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(MXC_V_UART_BAUD0_FACTOR_64 \
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<< MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */
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#define MXC_V_UART_BAUD0_FACTOR_32 \
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((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */
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#define MXC_S_UART_BAUD0_FACTOR_32 \
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(MXC_V_UART_BAUD0_FACTOR_32 \
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<< MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */
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#define MXC_V_UART_BAUD0_FACTOR_16 \
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((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */
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#define MXC_S_UART_BAUD0_FACTOR_16 \
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(MXC_V_UART_BAUD0_FACTOR_16 \
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<< MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */
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/**
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* Baud rate register. Decimal Setting.
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*/
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#define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */
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#define MXC_F_UART_BAUD1_DBAUD \
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((uint32_t)(0xFFFUL \
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<< MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */
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/**
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* FIFO Data buffer.
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*/
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#define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */
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#define MXC_F_UART_FIFO_FIFO \
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((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask \
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*/
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/**
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* DMA Configuration.
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*/
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#define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */
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#define MXC_F_UART_DMA_TDMA_EN \
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((uint32_t)( \
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0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */
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#define MXC_V_UART_DMA_TDMA_EN_DIS \
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((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */
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#define MXC_S_UART_DMA_TDMA_EN_DIS \
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(MXC_V_UART_DMA_TDMA_EN_DIS \
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<< MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */
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#define MXC_V_UART_DMA_TDMA_EN_EN \
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((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value \
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*/
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#define MXC_S_UART_DMA_TDMA_EN_EN \
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(MXC_V_UART_DMA_TDMA_EN_EN \
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<< MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */
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#define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */
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#define MXC_F_UART_DMA_RXDMA_EN \
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((uint32_t)(0x1UL \
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<< MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */
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#define MXC_V_UART_DMA_RXDMA_EN_DIS \
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((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */
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#define MXC_S_UART_DMA_RXDMA_EN_DIS \
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(MXC_V_UART_DMA_RXDMA_EN_DIS \
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<< MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */
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#define MXC_V_UART_DMA_RXDMA_EN_EN \
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((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */
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|
#define MXC_S_UART_DMA_RXDMA_EN_EN \
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|
(MXC_V_UART_DMA_RXDMA_EN_EN \
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<< MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */
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#define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */
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|
#define MXC_F_UART_DMA_TXDMA_LEVEL \
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|
((uint32_t)(0x3FUL \
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|
<< MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL \
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|
Mask */
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|
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#define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */
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|
#define MXC_F_UART_DMA_RXDMA_LEVEL \
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|
((uint32_t)(0x3FUL \
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|
<< MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL \
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|
Mask */
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|
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|
/**
|
|
* Transmit FIFO Status register.
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|
*/
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|
#define MXC_F_UART_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */
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|
#define MXC_F_UART_TX_FIFO_DATA \
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|
((uint32_t)(0x7FUL \
|
|
<< MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */
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|
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#endif /* _UART_REGS_H_ */
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