198 lines
5.6 KiB
C
198 lines
5.6 KiB
C
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_CHIP_H
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#define __CROS_EC_CONFIG_CHIP_H
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/* CPU core BFD configuration */
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#include "core/cortex-m/config_core.h"
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/* Number of IRQ vectors on the NVIC */
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#define CONFIG_IRQ_COUNT 157
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/* Use a bigger console output buffer */
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#undef CONFIG_UART_TX_BUF_SIZE
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#define CONFIG_UART_TX_BUF_SIZE 1024
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/* Interval between HOOK_TICK notifications */
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#define HOOK_TICK_INTERVAL_MS 250
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#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
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/*
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* Enable chip_pre_init called from main
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* Used for configuring peripheral block
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* sleep enables.
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*/
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#define CONFIG_CHIP_PRE_INIT
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/*
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* MCHP EC's have I2C master/slave
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* controllers and multiple I2C ports. Any
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* port may be mapped to any controller.
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* Enable multi-port controller feature.
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* Board level configuration determines
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* how many controllers/ports are used and
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* the mapping of port(s) to controller(s).
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* NOTE: Some MCHP reduced pin packages
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* may not implement all 11 I2C ports.
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*/
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#define CONFIG_I2C_MULTI_PORT_CONTROLLER
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/*
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* MCHP I2C controller is master-slave capable and requires
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* a slave address be programmed even if used as master only.
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* Each I2C controller can respond to two slave address.
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* Define dummy slave addresses that aren't used on the I2C port(s)
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* connected to each controller.
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*/
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#define CONFIG_MCHP_I2C0_SLAVE_ADDRS 0xE3E1
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#define CONFIG_MCHP_I2C1_SLAVE_ADDRS 0xE3E1
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#define CONFIG_MCHP_I2C2_SLAVE_ADDRS 0xE3E1
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#define CONFIG_MCHP_I2C3_SLAVE_ADDRS 0xE3E1
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/************************************************************************/
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/* Memory mapping */
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/*
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* MEC1701H has a total of 256KB SRAM.
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* CODE at 0xE0000 - 0x117FFF, DATA at 0x118000 - 0x11FFFF
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* MCHP MEC can fetch code from data or data from code.
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*/
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/************************************************************************/
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/* Define our RAM layout. */
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#define CONFIG_MEC_SRAM_BASE_START 0x000E0000
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#define CONFIG_MEC_SRAM_BASE_END 0x00120000
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#define CONFIG_MEC_SRAM_SIZE (CONFIG_MEC_SRAM_BASE_END - \
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CONFIG_MEC_SRAM_BASE_START)
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/* 64k Data RAM for RO / RW / loader */
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#define CONFIG_RAM_SIZE 0x00010000
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#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - \
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CONFIG_RAM_SIZE)
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/* System stack size */
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/* was 1024, temporarily expanded to 2048 for debug */
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#define CONFIG_STACK_SIZE 2048
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/* non-standard task stack sizes */
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/* temporarily expanded for debug */
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#define IDLE_TASK_STACK_SIZE 1024 /* 512 */
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#define LARGER_TASK_STACK_SIZE 1024 /* 640 */
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#define VENTI_TASK_STACK_SIZE 1024 /* 768 */
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#define CHARGER_TASK_STACK_SIZE 1024 /* 640 */
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#define HOOKS_TASK_STACK_SIZE 1024 /* 640 */
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#define CONSOLE_TASK_STACK_SIZE 1024 /* 640 */
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#define HOST_CMD_TASK_STACK_SIZE 1024 /* 640 */
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/*
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* TODO: Large stack consumption
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* https://code.google.com/p/chrome-os-partner/issues/detail?id=49245
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*/
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/* dsw original = 800, if stack exceptions expand to 1024 for debug */
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#define PD_TASK_STACK_SIZE 2048
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/* Default task stack size */
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#define TASK_STACK_SIZE 1024 /* 512 */
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/************************************************************************/
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/* Define our flash layout. */
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/* Protect bank size 4K bytes */
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#define CONFIG_FLASH_BANK_SIZE 0x00001000
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/* Sector erase size 4K bytes */
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#define CONFIG_FLASH_ERASE_SIZE 0x00001000
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/* Minimum write size */
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#define CONFIG_FLASH_WRITE_SIZE 0x00000004
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/* One page size for write */
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#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256
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/* Program memory base address */
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#define CONFIG_PROGRAM_MEMORY_BASE 0x000E0000
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#include "config_flash_layout.h"
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/************************************************************************/
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/* Customize the build */
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/* Optional features present on this chip */
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#define CONFIG_ADC
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#define CONFIG_DMA
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#define CONFIG_HOSTCMD_X86
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#define CONFIG_SPI
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#define CONFIG_SWITCH
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/*
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* Enable configuration after ESPI_RESET# de-asserts
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*/
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#undef CONFIG_MCHP_ESPI_RESET_DEASSERT_INIT
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/*
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* Enable CPRINT in chip eSPI module
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* Define at board level.
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*/
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#undef CONFIG_MCHP_ESPI_DEBUG
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/*
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* Enable EC UART commands in eSPI module useful for debugging.
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*/
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#undef CONFIG_MCHP_ESPI_EC_CMD
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/*
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* Enable CPRINT debug messages in LPC module
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*/
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#undef CONFIG_MCHP_DEBUG_LPC
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/*
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* Define this to use MEC1701 ROM SPI read API
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* in little firmware module instead of SPI code
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* from this module
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*/
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#undef CONFIG_CHIP_LFW_USE_ROM_SPI
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/*
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* Use DMA when transmitting commands & data
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* with GPSPI controllers.
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*/
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#define CONFIG_MCHP_GPSPI_TX_DMA
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/*
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* Use DMA when transmitting command & data of length
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* greater than QMSPI TX FIFO size.
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*/
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#define CONFIG_MCHP_QMSPI_TX_DMA
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/*
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* Board level gpio.inc is using MCHP data sheet GPIO pin
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* numbers which are octal.
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* MCHP has 6 banks/ports each containing 32 GPIO's.
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* Each bank/port is connected to a GIRQ.
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* Port numbering:
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* GPIO_015 = 13 decimal. Port = 13/32 = 0, bit = 13 % 32 = 13
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* GPIO_0123 = 83 decimal. Port 83/32 = 2, bit = 83 % 32 = 19
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* OR port = 0123 >> 5, bit = 0123 & 037(0x1F) = 023 = 19 decimal.
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* You must use octal GPIO numbers in PIN(gpio_num) macro in
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* gpio.inc files.
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* Example: GPIO 211 in documentation 0211 = 137 = 0x89
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* GPIO(PCH_SLP_S0_L, PIN(0211), GPIO_INPUT | GPIO_PULL_DOWN)
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* OR
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* GPIO(PCH_SLP_S0_L, PIN(0x89), GPIO_INPUT | GPIO_PULL_DOWN)
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*/
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#define GPIO_BANK(index) ((index) >> 5)
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#define GPIO_BANK_MASK(index) (1ul << ((index) & 0x1F))
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#define GPIO_PIN(index) GPIO_BANK(index), GPIO_BANK_MASK(index)
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#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
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#ifndef __ASSEMBLER__
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#endif /* #ifndef __ASSEMBLER__ */
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#endif /* __CROS_EC_CONFIG_CHIP_H */
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