298 lines
5.9 KiB
C
298 lines
5.9 KiB
C
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* QMSPI master module for MCHP MEC family */
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#include "common.h"
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#include "console.h"
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#include "dma.h"
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#include "gpio.h"
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#include "registers.h"
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#include "spi.h"
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#include "timer.h"
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#include "util.h"
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#include "hooks.h"
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#include "task.h"
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#include "spi_chip.h"
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#include "qmspi_chip.h"
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#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
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#include "gpspi_chip.h"
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#endif
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#include "tfdp_chip.h"
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#define CPUTS(outstr) cputs(CC_SPI, outstr)
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#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
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#define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
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#define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
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static const struct dma_option spi_rx_option[] = {
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{
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MCHP_DMAC_QMSPI0_RX,
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(void *)(MCHP_QMSPI0_RX_FIFO_ADDR),
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MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
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},
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#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
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#if CONFIG_MCHP_GPSPI & 0x01
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{
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MCHP_DMAC_SPI0_RX,
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(void *)&MCHP_SPI_RD(0),
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MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
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},
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#endif
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#if CONFIG_MCHP_GPSPI & 0x02
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{
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MCHP_DMAC_SPI1_RX,
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(void *)&MCHP_SPI_RD(1),
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MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
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},
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#endif
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#endif
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};
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static const struct dma_option spi_tx_option[] = {
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{
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MCHP_DMAC_QMSPI0_TX,
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(void *)(MCHP_QMSPI0_TX_FIFO_ADDR),
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MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
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},
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#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
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#if CONFIG_MCHP_GPSPI & 0x01
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{
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MCHP_DMAC_SPI0_TX,
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(void *)&MCHP_SPI_TD(0),
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MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
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},
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#endif
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#if CONFIG_MCHP_GPSPI & 0x02
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{
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MCHP_DMAC_SPI1_TX,
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(void *)&MCHP_SPI_TD(1),
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MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
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},
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#endif
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#endif
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};
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/* only regular image needs mutex, LFW does not have scheduling */
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#ifndef LFW
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static struct mutex spi_mutex[ARRAY_SIZE(spi_rx_option)];
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/*
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* Acquire mutex for specified SPI controller/port.
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* Note if mutex is owned by another task this routine
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* will block until mutex is released.
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*/
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static void spi_mutex_lock(uint8_t hw_port)
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{
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uint32_t n;
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n = 0;
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#ifdef CONFIG_MCHP_GPSPI
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if (hw_port & 0xF0) {
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#if (CONFIG_MCHP_GPSPI & 0x03) == 0x03
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n = (hw_port & 0x0F) + 1;
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#else
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n = 1;
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#endif
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}
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#endif
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mutex_lock(&spi_mutex[n]);
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}
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/*
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* Release mutex for specified SPI controller/port.
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*/
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static void spi_mutex_unlock(uint8_t hw_port)
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{
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uint32_t n;
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n = 0;
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#ifdef CONFIG_MCHP_GPSPI
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if (hw_port & 0xF0) {
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#if (CONFIG_MCHP_GPSPI & 0x03) == 0x03
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n = (hw_port & 0x0F) + 1;
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#else
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n = 1;
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#endif
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}
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#endif
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mutex_unlock(&spi_mutex[n]);
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}
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#endif /* #ifndef LFW */
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/*
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* Public SPI interface
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*/
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const void *spi_dma_option(const struct spi_device_t *spi_device,
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int is_tx)
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{
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uint32_t n;
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if (spi_device == NULL)
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return NULL;
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n = 0;
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#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
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if (spi_device->port & 0xF0) {
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#if (CONFIG_MCHP_GPSPI & 0x03) == 0x03
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n = (spi_device->port & 0x0F) + 1;
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#else
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n = 1;
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#endif
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}
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#endif
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if (is_tx)
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return &spi_tx_option[n];
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else
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return &spi_rx_option[n];
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}
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int spi_transaction_async(const struct spi_device_t *spi_device,
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const uint8_t *txdata, int txlen,
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uint8_t *rxdata, int rxlen)
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{
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int rc;
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if (spi_device == NULL)
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return EC_ERROR_INVAL;
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switch (spi_device->port) {
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#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
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case GPSPI0_PORT:
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case GPSPI1_PORT:
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rc = gpspi_transaction_async(spi_device, txdata,
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txlen, rxdata, rxlen);
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break;
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#endif
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case QMSPI0_PORT:
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rc = qmspi_transaction_async(spi_device, txdata,
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txlen, rxdata, rxlen);
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break;
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default:
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rc = EC_ERROR_INVAL;
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}
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return rc;
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}
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int spi_transaction_flush(const struct spi_device_t *spi_device)
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{
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int rc;
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if (spi_device == NULL)
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return EC_ERROR_INVAL;
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switch (spi_device->port) {
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#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
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case GPSPI0_PORT:
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case GPSPI1_PORT:
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rc = gpspi_transaction_flush(spi_device);
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break;
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#endif
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case QMSPI0_PORT:
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rc = qmspi_transaction_flush(spi_device);
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break;
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default:
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rc = EC_ERROR_INVAL;
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}
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return rc;
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}
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/* Wait for async response received but do not de-assert chip select */
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int spi_transaction_wait(const struct spi_device_t *spi_device)
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{
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int rc;
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if (spi_device == NULL)
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return EC_ERROR_INVAL;
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switch (spi_device->port) {
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#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
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#ifndef LFW
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case GPSPI0_PORT:
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case GPSPI1_PORT:
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rc = gpspi_transaction_wait(spi_device);
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break;
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#endif
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#endif
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case QMSPI0_PORT:
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rc = qmspi_transaction_wait(spi_device);
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break;
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default:
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rc = EC_ERROR_INVAL;
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}
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return rc;
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}
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/*
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* called from common/spi_flash.c
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* For tranfers reading less than the size of QMSPI RX FIFO call
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* a routine where reads use FIFO only no DMA.
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* GP-SPI only has a one byte RX FIFO but small data transfers will be OK
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* without the overhead of DMA setup.
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*/
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int spi_transaction(const struct spi_device_t *spi_device,
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const uint8_t *txdata, int txlen,
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uint8_t *rxdata, int rxlen)
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{
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int rc;
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if (spi_device == NULL)
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return EC_ERROR_PARAM1;
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#ifndef LFW
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spi_mutex_lock(spi_device->port);
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#endif
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rc = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
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if (rc == EC_SUCCESS)
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rc = spi_transaction_flush(spi_device);
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#ifndef LFW
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spi_mutex_unlock(spi_device->port);
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#endif
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return rc;
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}
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/**
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* Enable SPI port and associated controller
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*
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* @param port Zero based index into spi_device an array of
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* struct spi_device_t
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* @param enable
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* @return EC_SUCCESS or EC_ERROR_INVAL if port is unrecognized
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* @note called from common/spi_flash.c
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*
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* spi_devices[].port is defined as
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* bits[3:0] = controller instance
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* bits[7:4] = controller family 0 = QMSPI, 1 = GPSPI
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*/
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int spi_enable(int port, int enable)
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{
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int rc;
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uint8_t hw_port;
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rc = EC_ERROR_INVAL;
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if (port < spi_devices_used) {
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hw_port = spi_devices[port].port;
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if ((hw_port & 0xF0) == QMSPI_CLASS)
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rc = qmspi_enable(hw_port, enable);
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#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
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if ((hw_port & 0xF0) == GPSPI_CLASS)
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rc = gpspi_enable(hw_port, enable);
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#endif
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}
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return rc;
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}
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