180 lines
3.7 KiB
C
180 lines
3.7 KiB
C
/* Copyright 2018 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* SCP UART module */
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#include "clock_chip.h"
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#include "console.h"
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#include "registers.h"
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#include "serial_reg.h"
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#include "system.h"
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#include "task.h"
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#include "uart.h"
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#include "util.h"
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/* Console UART index */
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#define UARTN CONFIG_UART_CONSOLE
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#define UART_IDLE_WAIT_US 500
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static uint8_t uart_done, tx_started;
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int uart_init_done(void)
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{
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/*
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* TODO: AP UART support
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* When access AP UART port, wait for AP peripheral clock
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*/
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return uart_done;
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}
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void uart_tx_start(void)
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{
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tx_started = 1;
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/* AP UART mode doesn't support interrupt */
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if (UARTN >= SCP_UART_COUNT)
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return;
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if (UART_IER(UARTN) & UART_IER_THRI)
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return;
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disable_sleep(SLEEP_MASK_UART);
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UART_IER(UARTN) |= UART_IER_THRI;
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}
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void uart_tx_stop(void)
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{
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tx_started = 0;
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/* AP UART mode doesn't support interrupt */
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if (UARTN >= SCP_UART_COUNT)
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return;
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UART_IER(UARTN) &= ~UART_IER_THRI;
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enable_sleep(SLEEP_MASK_UART);
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}
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void uart_tx_flush(void)
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{
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while (!(UART_LSR(UARTN) & UART_LSR_TEMT))
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;
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}
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int uart_tx_ready(void)
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{
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/* Check xmit FIFO empty */
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return UART_LSR(UARTN) & UART_LSR_THRE;
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}
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int uart_rx_available(void)
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{
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/* Check rcvr data ready */
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return UART_LSR(UARTN) & UART_LSR_DR;
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}
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void uart_write_char(char c)
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{
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while (!uart_tx_ready())
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;
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UART_DATA(UARTN) = c;
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}
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int uart_read_char(void)
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{
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return UART_DATA(UARTN);
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}
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void uart_process(void)
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{
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uart_process_input();
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uart_process_output();
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}
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#if (UARTN < SCP_UART_COUNT)
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void uart_interrupt(void)
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{
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uint8_t ier;
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task_clear_pending_irq(UART_IRQ(UARTN));
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uart_process();
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ier = UART_IER(UARTN);
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UART_IER(UARTN) = 0;
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UART_IER(UARTN) = ier;
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}
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DECLARE_IRQ(UART_IRQ(UARTN), uart_interrupt, 2);
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void uart_rx_interrupt(void)
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{
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uint8_t ier;
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task_clear_pending_irq(UART_RX_IRQ(UARTN));
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SCP_INTC_UART_RX_IRQ &= ~BIT(UARTN);
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uart_process();
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ier = UART_IER(UARTN);
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UART_IER(UARTN) = 0;
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UART_IER(UARTN) = ier;
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SCP_INTC_UART_RX_IRQ |= 1 << UARTN;
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}
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DECLARE_IRQ(UART_RX_IRQ(UARTN), uart_rx_interrupt, 2);
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#endif
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void uart_task(void)
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{
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#if (UARTN >= SCP_UART_COUNT)
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while (1) {
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if (uart_rx_available() || tx_started)
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uart_process();
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else
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task_wait_event(UART_IDLE_WAIT_US);
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}
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#endif
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}
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void uart_init(void)
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{
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const uint32_t baud_rate = CONFIG_UART_BAUD_RATE;
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/*
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* UART clock source is set to ULPOSC1 / 10 below.
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*
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* TODO(b:134035444): We could get slightly more precise frequency by
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* using the _measured_ ULPOSC1 frequency (instead of the target).
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*/
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const uint32_t uart_clock = ULPOSC1_CLOCK_MHZ * 1000 / 10 * 1000;
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const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16);
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/* Init clock */
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#if UARTN == 0
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SCP_CLK_UART = CLK_UART_SEL_ULPOSC1_DIV10;
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SCP_CLK_GATE |= CG_UART_M | CG_UART_B | CG_UART_RSTN;
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#elif UARTN == 1
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SCP_CLK_UART = CLK_UART1_SEL_ULPOSC1_DIV10;
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SCP_CLK_GATE |= CG_UART1_M | CG_UART1_B | CG_UART1_RSTN;
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#endif
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/* Init and clear FIFO */
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UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO
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| UART_FCR_CLEAR_RCVR
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| UART_FCR_CLEAR_XMIT;
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/* Line control: parity none, 8 bit, 1 stop bit */
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UART_LCR(UARTN) = UART_LCR_WLEN8;
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/* For baud rate <= 115200 */
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UART_HIGHSPEED(UARTN) = 0;
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/* DLAB = 1 and update DLL DLH */
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UART_LCR(UARTN) |= UART_LCR_DLAB;
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UART_DLL(UARTN) = div & 0xff;
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UART_DLH(UARTN) = (div >> 8) & 0xff;
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UART_LCR(UARTN) &= ~UART_LCR_DLAB;
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UART_IER(UARTN) |= UART_IER_RDI;
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#if (UARTN < SCP_UART_COUNT)
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task_enable_irq(UART_IRQ(UARTN));
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task_enable_irq(UART_RX_IRQ(UARTN));
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/* UART RX IRQ needs an extra enable */
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SCP_INTC_UART_RX_IRQ |= 1 << UARTN;
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#endif
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gpio_config_module(MODULE_UART, 1);
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uart_done = 1;
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}
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