110 lines
4.1 KiB
C
110 lines
4.1 KiB
C
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_CHIP_NPCX7_H
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#define __CROS_EC_CONFIG_CHIP_NPCX7_H
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/*
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* NPCX7 Series Device-Specific Information
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* Ex. NPCX7(M)(N)(G/K/F)(B/C)
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* @param M: 8: 128-pins package, 9: 144-pins package
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* @param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size
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* @param G/K/F/W: Google EC depends on specific features.
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* @param B/C: (Optional) Chip generation in the same series.
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*/
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/*****************************************************************************/
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/* Hardware features */
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/* The optional hardware features depend on chip variant */
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#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
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defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
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defined(CHIP_VARIANT_NPCX7M7WC)
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#define NPCX_INT_FLASH_SUPPORT /* Internal flash support */
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#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */
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#define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */
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#endif
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#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
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defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
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#define NPCX_UART_FIFO_SUPPORT
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/* Number of UART modules. */
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#define NPCX_SECOND_UART
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#define UART_MODULE_COUNT 2
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#else
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#define UART_MODULE_COUNT 1
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#endif
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#if defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
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#define NPCX_WOV_SUPPORT /* Audio front-end for Wake-on-Voice support */
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#endif
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/*
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* Number of I2C controllers. Controller 4/5/6 has 2 ports, so the chip has
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* three additional ports.
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*/
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#define CONFIG_I2C_MULTI_PORT_CONTROLLER
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/* Number of I2C controllers */
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#define I2C_CONTROLLER_COUNT 8
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/* Number of I2C ports */
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#ifdef NPCX_PSL_MODE_SUPPORT
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#define I2C_PORT_COUNT 10
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#else
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#define I2C_PORT_COUNT 11
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#endif
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/* Use SHI module version 2 supported by npcx7 family */
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#define NPCX_SHI_V2
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/*****************************************************************************/
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/* Memory mapping */
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#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */
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#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
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defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G)
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#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
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/* 62 KB data RAM + 2 KB BT RAM size */
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#define CONFIG_DATA_RAM_SIZE 0x00010000
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#elif defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
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#define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */
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/* 126 KB data RAM + 2 KB BT RAM size */
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#define CONFIG_DATA_RAM_SIZE 0x00020000
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#endif
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#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
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/* no low power ram in npcx7 series */
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/* Use chip variant to specify the size and start address of program memory */
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#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
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defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G)
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/* 192KB RAM for FW code */
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#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
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/* program memory base address for 192KB Code RAM (ie. 0x100C0000 - 192KB) */
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#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
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#elif defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
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/* 256KB RAM for FW code */
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#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024)
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/* program memory base address for 256KB Code RAM (ie. 0x100B0000 - 256KB) */
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#define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
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#else
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#error "Unsupported chip variant"
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#endif
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/* Total RAM size checking for npcx ec */
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#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
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#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
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defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G)
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/* 256KB RAM in NPCX7M6F/NPCX7M6FB/NPCX7M6FC/NPCX7M6G */
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#if (NPCX_RAM_SIZE != 0x40000)
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#error "Wrong memory mapping layout for NPCX7M6F"
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#endif
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#elif defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
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/* 384KB RAM in NPCX7M7WB/NPCX7M7WC */
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#if (NPCX_RAM_SIZE != 0x60000)
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#error "Wrong memory mapping layout for NPCX7M7W"
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#endif
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#endif
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#endif /* __CROS_EC_CONFIG_CHIP_NPCX7_H */
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