659 lines
16 KiB
C
659 lines
16 KiB
C
/* Copyright 2018 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_WOV_CHIP_H
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#define __CROS_EC_WOV_CHIP_H
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#include "common.h"
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/* FMUL2 clock Frequency. */
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enum fmul2_clk_freq {
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FMUL2_48_MHZ = 0, /* Default */
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FMUL2_24_MHZ
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};
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enum fmul2_clk_divider {
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FMUL2_CLK_NO_DIVIDER = 0x00,
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FMUL2_CLK_DIVIDER_BY_2 = 0x01,
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FMUL2_CLK_DIVIDER_BY_4 = 0x03, /* Default */
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FMUL2_CLK_DIVIDER_BY_8 = 0x07
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};
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/* Microphone source. */
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enum wov_mic_source {
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/* Only data from left mic. */
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WOV_SRC_LEFT = 0,
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/* Only data from right mic. */
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WOV_SRC_RIGHT,
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/* Both channels have the same data (average of left & right */
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WOV_SRC_MONO,
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/* Each channel has its own data. */
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WOV_SRC_STEREO
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};
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/* Clock source for APM. */
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enum wov_clk_src_sel {
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WOV_FMUL2_CLK_SRC = 0,
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WOV_PLL_CLK_SRC = 1
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};
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/* FMUL clock division factore. */
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enum wov_fmul_div {
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WOV_NODIV = 0,
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WOV_DIV_BY_2,
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WOV_DIV_BY_4, /* Default value */
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WOV_DIV_BY_8
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};
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/* Lock state. */
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enum wov_lock_state {
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WOV_UNLOCK = 0,
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WOV_LOCK = 1
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};
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/* Reference clock source select. */
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enum wov_ref_clk_src_sel {
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WOV_FREE_RUN_OSCILLATOR = 0,
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WOV_CRYSTAL_OSCILLATOR = 1
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};
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/* PLL external divider select. */
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enum wov_ext_div_sel {
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WOV_EXT_DIV_BINARY_CNT = 0,
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WOV_EXT_DIV_LFSR_DIV = 1
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};
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/* FMUL output frequency. */
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enum wov_fmul_out_freq {
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WOV_FMUL_OUT_FREQ_48_MHZ = 0,
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WOV_FMUL_OUT_FREQ_49_MHZ = 1
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};
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/* Digital microphone clock divider select. */
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enum wov_dmic_clk_div_sel {
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WOV_DMIC_DIV_DISABLE = 1,
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WOV_DMIC_DIV_BY_2 = 2,
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WOV_DMIC_DIV_BY_4 = 4
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};
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/* FIFO threshold. */
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enum wov_fifo_threshold {
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WOV_FIFO_THRESHOLD_1_DATA_WORD = 0,
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WOV_FIFO_THRESHOLD_2_DATA_WORDS = 1,
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WOV_FIFO_THRESHOLD_4_DATA_WORDS = 2,
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WOV_FIFO_THRESHOLD_8_DATA_WORDS = 4,
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WOV_FIFO_THRESHOLD_16_DATA_WORDS = 8,
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WOV_FIFO_THRESHOLD_32_DATA_WORDS = 16,
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WOV_FIFO_THRESHOLD_40_DATA_WORDS = 20,
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WOV_FIFO_THRESHOLD_64_DATA_WORDS = 32,
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WOV_FIFO_THRESHOLD_80_DATA_WORDS = 40,
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WOV_FIFO_THRESHOLD_96_DATA_WORDS = 48
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};
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/* FIFO DMA request select. */
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enum wov_fifo_dma_req_sel {
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WOV_FIFO_DMA_DFLT_DMA_REQ_CONN = 0,
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WOV_FIFO_DMA_DMA_REQ_CON_FIFO
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};
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/* FIFO operational state. */
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enum wov_fifo_oper_state {
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WOV_FIFO_OPERATIONAL = 0,
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WOV_FIFO_RESET, /* Default */
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};
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/* WoV interrupt index. */
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enum wov_interrupt_index {
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WOV_VAD_INT_INDX,
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WOV_VAD_WAKE_INDX,
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WOV_CFIFO_NOT_EMPTY_INDX,
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WOV_CFIFO_THRESHOLD_INT_INDX,
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WOV_CFIFO_THRESHOLD_WAKE_INDX,
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WOV_CFIFO_OVERRUN_INT_INDX,
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WOV_I2SFIFO_OVERRUN_INT_INDX,
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WOV_I2SFIFO_UNDERRUN_INT_INDX
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};
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/* FIFO DMA request selection. */
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enum wov_dma_req_sel {
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WOV_DFLT_ESPI_DMA_REQ = 0,
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WOV_FROM_FIFO_DMA_REQUEST
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};
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/* Core FIFO input select. */
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enum wov_core_fifo_in_sel {
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WOV_CFIFO_IN_LEFT_CHAN_2_CONS_16_BITS = 0, /* Default */
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WOV_CFIFO_IN_LEFT_RIGHT_CHAN_16_BITS,
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WOV_CFIFO_IN_LEFT_CHAN_24_BITS,
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WOV_CFIFO_IN_LEFT_RIGHT_CHAN_24_BITS
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};
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/* PLL external divider selector. */
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enum wov_pll_ext_div_sel {
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WOV_PLL_EXT_DIV_BIN_CNT = 0,
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WOV_PLL_EXT_DIV_LFSR
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};
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/* Code for events for call back function. */
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enum wov_events {
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WOV_NO_EVENT = 0,
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/*
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* Data is ready.
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* need to call to wov_set_buffer to update the buffer * pointer
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*/
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WOV_EVENT_DATA_READY = 1,
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WOV_EVENT_VAD, /* Voice activity detected */
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WOV_EVENT_ERROR_FIRST = 128,
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WOV_EVENT_ERROR_CORE_FIFO_OVERRUN = 128,
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WOV_EVENT_ERROR_I2S_FIFO_UNDERRUN = 129,
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WOV_EVENT_ERROR_I2S_FIFO_OVERRUN = 130,
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WOV_EVENT_ERROR_LAST = 255,
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};
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/* WoV FIFO errors. */
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enum wov_fifo_errors {
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WOV_FIFO_NO_ERROR = 0,
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WOV_CORE_FIFO_OVERRUN = 1, /* 2 : I2S FIFO is underrun. */
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WOV_I2S_FIFO_OVERRUN = 2, /* 3 : I2S FIFO is overrun. */
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WOV_I2S_FIFO_UNDERRUN = 3 /* 4 : I2S FIFO is underrun. */
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};
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/* Selects I2S test mode. */
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enum wov_test_mode { WOV_NORMAL_MODE = 0, WOV_TEST_MODE };
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/* PULL_UP/PULL_DOWN selection. */
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enum wov_pull_upd_down_sel { WOV_PULL_DOWN = 0, WOV_PULL_UP };
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/* I2S output data floating mode. */
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enum wov_floating_mode { WOV_FLOATING_DRIVEN = 0, WOV_FLOATING };
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/* Clock inverted mode. */
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enum wov_clk_inverted_mode { WOV_CLK_NORMAL = 0, WOV_CLK_INVERTED };
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enum wov_i2s_chan_trigger {
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WOV_I2S_SAMPLED_1_AFTER_0 = 0,
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WOV_I2S_SAMPLED_0_AFTER_1 = 1
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};
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/* APM modes. */
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enum wov_modes {
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WOV_MODE_OFF = 1,
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WOV_MODE_VAD,
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WOV_MODE_RAM,
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WOV_MODE_I2S,
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WOV_MODE_RAM_AND_I2S
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};
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/* DAI format. */
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enum wov_dai_format {
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WOV_DAI_FMT_I2S, /* I2S mode */
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WOV_DAI_FMT_RIGHT_J, /* Right Justified mode */
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WOV_DAI_FMT_LEFT_J, /* Left Justified mode */
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WOV_DAI_FMT_PCM_A, /* PCM A Audio */
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WOV_DAI_FMT_PCM_B, /* PCM B Audio */
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WOV_DAI_FMT_PCM_TDM /* Time Division Multiplexing */
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};
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struct wov_config {
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enum wov_modes mode;
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uint32_t sample_per_sec;
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int bit_depth;
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enum wov_mic_source mic_src;
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int left_chan_gain;
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int right_chan_gain;
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uint16_t i2s_start_delay_0;
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uint16_t i2s_start_delay_1;
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uint32_t i2s_clock;
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enum wov_dai_format dai_format;
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int sensitivity_db;
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};
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extern struct wov_config wov_conf;
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/**
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* Set FMUL2 clock divider.
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*
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* @param None
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* @return None
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*/
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void wov_fmul2_set_clk_divider(enum fmul2_clk_divider clk_div);
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/**
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* WoV Call back function decleration.
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*
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* @param event - the event that cause the call to the callback
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* function.
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*
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* @return None
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*/
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typedef void (*wov_call_back_t)(enum wov_events);
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/*
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* WoV macros.
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*/
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/* MACROs that set fields of the Clock Control Register structure. */
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#define WOV_APM_CLK_SRC_FMUL2(reg_val) reg_val.clk_sel = 0
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#define WOV_APM_CLK_SRC_PLL(reg_val) reg_val.clk_sel = 1
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#define WOV_APM_GET_CLK_SRC(reg_val) (reg_val.clk_sel)
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/* Core FIFO threshold. */
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#define WOV_GET_CORE_FIFO_THRESHOLD WOV_GET_FIFO_INT_THRESHOLD
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/******************************************************************************
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*
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* WoV APIs
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*
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******************************************************************************/
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/**
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* Initiates WoV.
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*
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* @param callback - Pointer to callback function.
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*
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* @return None
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*/
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void wov_init(void);
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/**
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* Sets WoV stage
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*
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* @param wov_mode - WoV stage (Table 38)
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* @return EC_ERROR_INVAL or EC_SUCCESS
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*/
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enum ec_error_list wov_set_mode(enum wov_modes wov_mode);
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/**
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* Gets WoV mode
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*
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* @param None
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* @return WoV mode
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*/
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enum wov_modes wov_get_mode(void);
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/**
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* Configure WoV.
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*
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* @param samples_per_second - Valid sample rate.
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* @return In case sample rate is valid return EC_SUCCESS othewise return
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* error code.
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*/
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int wov_set_sample_rate(uint32_t samples_per_second);
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/**
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* Gets sampling rate.
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*
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* @param None
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* @return the current sampling rate.
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*/
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uint32_t wov_get_sample_rate(void);
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/**
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* Sets sampling depth.
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*
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* @param bits_num - Valid sample depth in bits.
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* @return In case sample depth is valid return EC_SUCCESS othewise return
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* error code.
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*/
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int wov_set_sample_depth(int bits_num);
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/**
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* Gets sampling depth.
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*
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* @param None.
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* @return sample depth in bits.
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*/
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int wov_get_sample_depth(void);
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/**
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* Sets microphone source.
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*
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* @param mic_src - Valid microphone source
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* @return return EC_SUCCESS if mic source valid othewise
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* return error code.
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*/
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int wov_set_mic_source(enum wov_mic_source mic_src);
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/**
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* Gets microphone source.
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*
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* @param None.
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* @return sample depth in bits.
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*/
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enum wov_mic_source wov_get_mic_source(void);
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/**
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* Mutes the WoV.
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*
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* @param enable - enabled flag, true means enable
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* @return None
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*/
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void wov_mute(int enable);
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/**
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* Gets gain values
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*
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* @param left_chan_gain - address of left channel gain response.
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* @param right_chan_gain - address of right channel gain response.
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* @return None
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*/
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void wov_get_gain(int *left_chan_gain, int *right_chan_gain);
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/**
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* Sets gain
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*
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* @param left_chan_gain - Left channel gain.
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* @param right_chan_gain - Right channel gain
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* @return None
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*/
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void wov_set_gain(int left_chan_gain, int right_chan_gain);
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/**
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* Enables/Disables ADC.
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*
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* @param enable - enabled flag, true means enable
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* @return None
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*/
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void wov_enable_agc(int enable);
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/**
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* Enables/Disables the automatic gain.
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*
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* @param stereo - Stereo enabled flag, 1 means enable.
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* @param target - Target output level of the ADC.
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* @param noise_gate_threshold - Noise Gate system select. 1 means enable.
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* @param hold_time - Hold time before starting AGC adjustment to
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* the TARGET value.
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* @param attack_time - Attack time - gain ramp down.
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* @param decay_time - Decay time - gain ramp up.
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* @param max_applied_gain - Maximum Gain Value to apply to the ADC path.
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* @param min_applied_gain - Minimum Gain Value to apply to the ADC path.
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* @return EC_ERROR_INVAL or EC_SUCCESS
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*/
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enum ec_error_list wov_set_agc_config(int stereo, float target,
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int noise_gate_threshold, uint8_t hold_time,
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uint16_t attack_time, uint16_t decay_time,
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float max_applied_gain, float min_applied_gain);
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/**
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* Sets VAD sensitivity.
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*
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* @param sensitivity_db - VAD sensitivity in db.
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* @return None
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*/
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int wov_set_vad_sensitivity(int sensitivity_db);
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/**
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* Gets VAD sensitivity.
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*
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* @param None.
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* @return VAD sensitivity in db
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*/
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int wov_get_vad_sensitivity(void);
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/**
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* Configure I2S bus format. (Sample rate and size are determined via common
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* config functions.)
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*
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* @param format - one of the following: I2S mode, Right Justified mode,
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* Left Justified mode, PCM A Audio, PCM B Audio and
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* Time Division Multiplexing
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* @return EC error code.
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*/
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void wov_set_i2s_fmt(enum wov_dai_format format);
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/**
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* Configure I2S bus clock. (Sample rate and size are determined via common
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* config functions.)
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*
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* @param i2s_clock - I2S clock frequency in Hz (needed in order to
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* configure the internal PLL for 12MHz)
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* @return EC error code.
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*/
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void wov_set_i2s_bclk(uint32_t i2s_clock);
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/**
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* Configure I2S bus. (Sample rate and size are determined via common
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* config functions.)
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*
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* @param ch0_delay - 0 to 496. Defines the delay from the SYNC till the
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* first bit (MSB) of channel 0 (left channel)
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* @param ch1_delay - -1 to 496. Defines the delay from the SYNC till the
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* first bit (MSB) of channel 1 (right channel).
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* If channel 1 is not used set this field to -1.
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*
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* @param flags - WOV_TDM_ADJACENT_TO_CH0 = BIT(0). There is a
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* channel adjacent to channel 0, so float SDAT when
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* driving the last bit (LSB) of the channel during the
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* second half of the clock cycle to avoid bus contention.
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*
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* WOV_TDM_ADJACENT_TO_CH1 = BIT(1). There is a channel
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* adjacent to channel 1.
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*
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* @return EC error code.
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*/
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enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay,
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uint32_t flags);
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/**
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* Configure FMUL2 clock tunning.
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*
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* @param None
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* @return None
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*/
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void wov_fmul2_conf_tuning(void);
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/**
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* Configure DMIC clock.
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*
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* @param enable - DMIC enabled , true means enable
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* @param clk_div - DMIC clock division factor (disable, divide by 2
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* divide by 4)
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* @return None
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*/
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void wov_dmic_clk_config(int enable, enum wov_dmic_clk_div_sel clk_div);
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/**
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* FMUL2 clock control configuration.
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*
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* @param clk_src - select between FMUL2 (WOV_FMUL2_CLK_SRC) and
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* PLL (WOV_PLL_CLK_SRC)
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* @return None
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*/
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extern void wov_set_clk_selection(enum wov_clk_src_sel clk_src);
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/**
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* Configure PLL clock.
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*
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* @param ext_div_sel - PLL external divider selector.
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* @param div_factor - When ext_div_sel is WOV_PLL_EXT_DIV_BIN_CNT
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* then it is the 4 LSBits of this field,
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* otherwise this field is an index to
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* PLL External Divider Load Values table.
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* @return EC_ERROR_INVAL or EC_SUCCESS
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*/
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enum ec_error_list wov_pll_clk_ext_div_config(
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enum wov_pll_ext_div_sel ext_div_sel, uint32_t div_factor);
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/**
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* PLL power down.
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*
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* @param enable - true power down the PLL or false PLL operating
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* @return None
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*/
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void wov_pll_enable(int enable);
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/**
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* Configures PLL clock dividers..
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*
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* @param out_div_1 - PLL output divider #1, valid values 1-7
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* @param out_div_2 - PLL output divider #2, valid values 1-7
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* @param feedback_div - PLL feadback divider (Default is 375 decimal)
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* @param in_div - PLL input divider
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* @return EC_ERROR_INVAL or EC_SUCCESS
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*/
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enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1,
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uint32_t out_div_2,
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uint32_t feedback_div,
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uint32_t in_div);
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/**
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* Enables/Disables WoV interrupt.
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*
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* @param int_index - Interrupt ID.
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* @param enable - enabled flag, 1 means enable
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*
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* @return None.
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*/
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void wov_interrupt_enable(enum wov_interrupt_index int_index, int enable);
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|
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/**
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|
* Sets core FIFO threshold.
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|
*
|
|
* @param in_sel - Core FIFO input select
|
|
* @param threshold - Core FIFO threshold
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|
*
|
|
* @return None
|
|
*/
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void wov_cfifo_config(enum wov_core_fifo_in_sel in_sel,
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enum wov_fifo_threshold threshold);
|
|
|
|
/**
|
|
* Start the actual capturing of the Voice data to the RAM.
|
|
* Note that the pointer to the RAM buffer must be precisely
|
|
* set by calling wov_set_buffer();
|
|
*
|
|
* @param None
|
|
*
|
|
* @return None
|
|
*/
|
|
void wov_start_ram_capture(void);
|
|
|
|
/**
|
|
* Stop the capturing of the Voice data to the RAM.
|
|
*
|
|
* @param none
|
|
*
|
|
* @return None
|
|
*/
|
|
void wov_stop_ram_capture(void);
|
|
|
|
/**
|
|
* Rests the Core FIFO.
|
|
*
|
|
* @param None
|
|
*
|
|
* @return None
|
|
*/
|
|
void wov_core_fifo_reset(void);
|
|
|
|
/**
|
|
* Rests the I2S FIFO.
|
|
*
|
|
* @param None
|
|
*
|
|
* @return None
|
|
*/
|
|
void wov_i2s_fifo_reset(void);
|
|
|
|
/**
|
|
* Start the capturing of the Voice data via I2S.
|
|
*
|
|
* @param None
|
|
*
|
|
* @return None
|
|
*/
|
|
void wov_start_i2s_capture(void);
|
|
|
|
/**
|
|
* Stop the capturing of the Voice data via I2S.
|
|
*
|
|
* @param none
|
|
*
|
|
* @return None
|
|
*/
|
|
void wov_stop_i2s_capture(void);
|
|
|
|
/**
|
|
* Reads data from the core fifo.
|
|
*
|
|
* @param num_elements - Number of elements (Dword) to read.
|
|
*
|
|
* @return None
|
|
*/
|
|
void wov_cfifo_read_handler(uint32_t num_elements);
|
|
|
|
/**
|
|
* Sets data buffer for reading from core FIFO
|
|
*
|
|
* @param buff - Pointer to the read buffer, buffer must be 32 bits
|
|
* aligned.
|
|
* @param size_in_words - Size must be a multiple of CONFIG_WOV_THRESHOLD_WORDS
|
|
* (defaulte = 80 words)
|
|
*
|
|
* @return None
|
|
*
|
|
* Note - When the data buffer will be full the FW will be notifyed
|
|
* about it, and the FW will need to recall to this function.
|
|
*/
|
|
int wov_set_buffer(uint32_t *buff, int size_in_words);
|
|
|
|
/**
|
|
* Resets the APM.
|
|
*
|
|
* @param enable - enabled flag, true or false
|
|
* @return None
|
|
*/
|
|
void wov_apm_active(int enable);
|
|
|
|
void wov_handle_event(enum wov_events event);
|
|
|
|
/**
|
|
* I2S golobal configuration
|
|
*
|
|
* @param i2s_hiz_data - Defines when the I2S data output is floating.
|
|
* @param i2s_hiz - Defines if the I2S data output is always floating.
|
|
* @param clk_invert - Defines the I2S bit clock edge sensitivity
|
|
* @param out_pull_en - Enable a pull-up or a pull-down resistor on
|
|
* I2S output
|
|
* @param out_pull_mode - Select a pull-up or a pull-down resistor on
|
|
* I2S output
|
|
* @param in_pull_en - Enable a pull-up or a pull-down resistor on
|
|
* I2S input
|
|
* @param in_pull_mode - Select a pull-up or a pull-down resistor on
|
|
* I2S intput
|
|
* @param test_mode - Selects I2S test mode
|
|
*
|
|
* @return EC_ERROR_INVAL or EC_SUCCESS
|
|
*/
|
|
enum ec_error_list wov_i2s_global_config(
|
|
enum wov_floating_mode i2s_hiz_data,
|
|
enum wov_floating_mode i2s_hiz,
|
|
enum wov_clk_inverted_mode clk_invert,
|
|
int out_pull_en, enum wov_pull_upd_down_sel out_pull_mode,
|
|
int in_pull_en,
|
|
enum wov_pull_upd_down_sel in_pull_mode,
|
|
enum wov_test_mode test_mode);
|
|
|
|
/**
|
|
* I2S channel configuration
|
|
*
|
|
* @param channel_num - I2S channel number, 0 or 1.
|
|
* @param bit_count - I2S channel bit count.
|
|
* @param trigger - Define the I2S chanel trigger 1->0 or 0->1
|
|
* @param start_delay - Defines the delay from the trigger defined for
|
|
* the channel till the first bit (MSB) of the data.
|
|
*
|
|
* @return EC_ERROR_INVAL or EC_SUCCESS
|
|
*/
|
|
enum ec_error_list wov_i2s_channel_config(uint32_t channel_num,
|
|
uint32_t bit_count, enum wov_i2s_chan_trigger trigger,
|
|
int32_t start_delay);
|
|
|
|
#endif /* __CROS_EC_WOV_CHIP_H */
|