172 lines
3.3 KiB
C
172 lines
3.3 KiB
C
/* Copyright 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "adc.h"
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#include "adc_chip.h"
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#include "common.h"
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#include "console.h"
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#include "clock.h"
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#include "dma.h"
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#include "hooks.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */
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struct mutex adc_lock;
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static int restore_clock;
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static inline void adc_set_channel(int sample_id, int channel)
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{
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uint32_t mask, val;
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volatile uint32_t *sqr_reg;
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int reg_id;
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reg_id = 5 - sample_id / 6;
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mask = 0x1f << ((sample_id % 6) * 5);
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val = channel << ((sample_id % 6) * 5);
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sqr_reg = &STM32_ADC_SQR(reg_id);
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*sqr_reg = (*sqr_reg & ~mask) | val;
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}
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static void adc_configure(int ain_id)
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{
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/* Set ADC channel */
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adc_set_channel(0, ain_id);
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/* Disable DMA */
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STM32_ADC_CR2 &= ~BIT(8);
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/* Disable scan mode */
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STM32_ADC_CR1 &= ~BIT(8);
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}
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static void adc_configure_all(void)
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{
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int i;
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/* Set ADC channels */
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STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20;
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for (i = 0; i < ADC_CH_COUNT; ++i)
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adc_set_channel(i, adc_channels[i].channel);
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/* Enable DMA */
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STM32_ADC_CR2 |= BIT(8);
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/* Enable scan mode */
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STM32_ADC_CR1 |= BIT(8);
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}
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static inline int adc_powered(void)
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{
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return STM32_ADC_SR & BIT(6); /* ADONS */
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}
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static void adc_enable_clock(void)
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{
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STM32_RCC_APB2ENR |= BIT(9);
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/* ADCCLK = HSI / 2 = 8MHz*/
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STM32_ADC_CCR |= BIT(16);
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}
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static void adc_init(void)
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{
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/*
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* For STM32L, ADC clock source is HSI/2 = 8 MHz. HSI must be enabled
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* for ADC.
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*
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* Note that we are not powering on ADC on EC initialization because
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* STM32L ADC module requires HSI clock. Instead, ADC module is powered
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* on/off in adc_prepare()/adc_release().
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*/
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/* Enable ADC clock. */
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adc_enable_clock();
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if (!adc_powered())
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/* Power on ADC module */
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STM32_ADC_CR2 |= BIT(0); /* ADON */
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/* Set right alignment */
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STM32_ADC_CR2 &= ~BIT(11);
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/*
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* Set sample time of all channels to 16 cycles.
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* Conversion takes (12+16)/8M = 3.34 us.
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*/
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STM32_ADC_SMPR1 = 0x24924892;
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STM32_ADC_SMPR2 = 0x24924892;
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STM32_ADC_SMPR3 = 0x24924892;
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}
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static void adc_prepare(void)
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{
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if (!adc_powered()) {
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clock_enable_module(MODULE_ADC, 1);
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adc_init();
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restore_clock = 1;
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}
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}
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static void adc_release(void)
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{
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if (restore_clock) {
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clock_enable_module(MODULE_ADC, 0);
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restore_clock = 0;
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}
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/*
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* Power down the ADC. The ADC consumes a non-trivial amount of power,
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* so it's wasteful to leave it on.
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*/
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if (adc_powered())
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STM32_ADC_CR2 = 0;
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}
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static inline int adc_conversion_ended(void)
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{
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return STM32_ADC_SR & BIT(1);
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}
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int adc_read_channel(enum adc_channel ch)
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{
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const struct adc_t *adc = adc_channels + ch;
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int value;
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timestamp_t deadline;
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mutex_lock(&adc_lock);
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adc_prepare();
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adc_configure(adc->channel);
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/* Clear EOC bit */
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STM32_ADC_SR &= ~BIT(1);
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/* Start conversion */
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STM32_ADC_CR2 |= BIT(30); /* SWSTART */
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/* Wait for EOC bit set */
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deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT;
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value = ADC_READ_ERROR;
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do {
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if (adc_conversion_ended()) {
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value = STM32_ADC_DR & ADC_READ_MAX;
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break;
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}
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} while (!timestamp_expired(deadline, NULL));
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adc_release();
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mutex_unlock(&adc_lock);
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return (value == ADC_READ_ERROR) ? ADC_READ_ERROR :
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value * adc->factor_mul / adc->factor_div + adc->shift;
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}
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