74 lines
2.6 KiB
C
74 lines
2.6 KiB
C
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Memory mapping */
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#define CONFIG_FLASH_SIZE (2048 * 1024)
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#define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */
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/* always use 256-bit writes due to ECC */
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#define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */
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#define CONFIG_FLASH_WRITE_IDEAL_SIZE 32
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/*
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* What the code is calling 'bank' is really the size of the block used for
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* write-protected, here it's 128KB sector (same as erase size).
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*/
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#define CONFIG_FLASH_BANK_SIZE (128 * 1024)
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/* Erasing 128K can take up to 2s, need to defer erase. */
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#define CONFIG_FLASH_DEFERRED_ERASE
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/* ITCM-RAM: 64kB 0x00000000 - 0x0000FFFF (CPU and MDMA) */
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/* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF (CPU and MDMA) */
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/* (D1) AXI-SRAM : 512kB 0x24000000 - 0x2407FFFF (no BDMA) */
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/* (D2) AHB-SRAM1: 128kB 0x30000000 - 0x3001FFFF */
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/* (D2) AHB-SRAM2: 128kB 0x30020000 - 0x3003FFFF */
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/* (D2) AHB-SRAM3: 32kB 0x30040000 - 0x30047FFF */
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/* (D3) AHB-SRAM4: 64kB 0x38000000 - 0x3800FFFF */
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/* (D3) backup RAM: 4kB 0x38800000 - 0x38800FFF */
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#define CONFIG_RAM_BASE 0x24000000
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#define CONFIG_RAM_SIZE 0x00080000
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#define CONFIG_RO_MEM_OFF 0
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#define CONFIG_RO_SIZE (128 * 1024)
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#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE / 2)
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#define CONFIG_RW_SIZE (512 * 1024)
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#define CONFIG_RO_STORAGE_OFF 0
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#define CONFIG_RW_STORAGE_OFF 0
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#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
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#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
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(CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF)
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#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
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#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
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#undef I2C_PORT_COUNT
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#define I2C_PORT_COUNT 4
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/*
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* Cannot use PSTATE:
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* 128kB blocks are too large and ECC prevents re-writing PSTATE word.
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*/
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#undef CONFIG_FLASH_PSTATE
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#undef CONFIG_FLASH_PSTATE_BANK
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/* Number of IRQ vectors on the NVIC */
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#define CONFIG_IRQ_COUNT 150
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/* the Cortex-M7 core has 'standard' ARMv7-M caches */
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#define CONFIG_ARMV7M_CACHE
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/* Use the MPU to configure cacheability */
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#define CONFIG_MPU
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/* Store in uncached buffers for DMA transfers in ahb4 region */
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#define CONFIG_CHIP_UNCACHED_REGION ahb4
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/* Override MPU attribute settings to match the chip requirements */
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/* Code is Normal memory type / non-shareable / write-through */
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#define MPU_ATTR_FLASH_MEMORY 0x02
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/* SRAM Data is Normal memory type / non-shareable / write-back, write-alloc */
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#define MPU_ATTR_INTERNAL_SRAM 0x0B
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