52 lines
1.1 KiB
C
52 lines
1.1 KiB
C
/* Copyright 2019 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Registers map and definitions for RISC-V cores
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*/
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#ifndef __CROS_EC_CPU_H
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#define __CROS_EC_CPU_H
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#ifdef CONFIG_FPU
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/* additional space to save FP registers (fcsr, ft0-11, fa0-7, fs0-11) */
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#define TASK_SCRATCHPAD_SIZE (62)
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#else
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#define TASK_SCRATCHPAD_SIZE (29)
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#endif
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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/* write Exception Program Counter register */
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static inline void set_mepc(uint32_t val)
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{
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asm volatile ("csrw mepc, %0" : : "r"(val));
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}
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/* read Exception Program Counter register */
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static inline uint32_t get_mepc(void)
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{
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uint32_t ret;
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asm volatile ("csrr %0, mepc" : "=r"(ret));
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return ret;
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}
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/* read Trap cause register */
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static inline uint32_t get_mcause(void)
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{
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uint32_t ret;
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asm volatile ("csrr %0, mcause" : "=r"(ret));
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return ret;
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}
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/* Generic CPU core initialization */
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void cpu_init(void);
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extern uint32_t ec_reset_lp;
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extern uint32_t ira;
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#endif
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#endif /* __CROS_EC_CPU_H */
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