166 lines
6.1 KiB
C
166 lines
6.1 KiB
C
/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* BMA2x2 gsensor module for Chrome EC */
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#ifndef __CROS_EC_ACCEL_BMA2x2_H
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#define __CROS_EC_ACCEL_BMA2x2_H
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extern const struct accelgyro_drv bma2x2_accel_drv;
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/* I2C ADDRESS DEFINITIONS */
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/* The following definition of I2C address is used for the following sensors
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* BMA255
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* BMA355
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* BMA280
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* BMA282
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* BMA223
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* BMA254
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* BMA284
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* BMA250E
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* BMA222E
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*/
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#define BMA2x2_I2C_ADDR1_FLAGS 0x18
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#define BMA2x2_I2C_ADDR2_FLAGS 0x19
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/* The following definition of I2C address is used for the following sensors
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* BMC150
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* BMC056
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* BMC156
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*/
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#define BMA2x2_I2C_ADDR3_FLAGS 0x10
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#define BMA2x2_I2C_ADDR4_FLAGS 0x11
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/*** Chip-specific registers ***/
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/* REGISTER ADDRESS DEFINITIONS */
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#define BMA2x2_EEP_OFFSET 0x16
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#define BMA2x2_IMAGE_BASE 0x38
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#define BMA2x2_IMAGE_LEN 22
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#define BMA2x2_CHIP_ID_ADDR 0x00
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#define BMA255_CHIP_ID_MAJOR 0xfa
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/* DATA ADDRESS DEFINITIONS */
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#define BMA2x2_X_AXIS_LSB_ADDR 0x02
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#define BMA2x2_X_AXIS_MSB_ADDR 0x03
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#define BMA2x2_Y_AXIS_LSB_ADDR 0x04
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#define BMA2x2_Y_AXIS_MSB_ADDR 0x05
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#define BMA2x2_Z_AXIS_LSB_ADDR 0x06
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#define BMA2x2_Z_AXIS_MSB_ADDR 0x07
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#define BMA2x2_TEMP_ADDR 0x08
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/* STATUS ADDRESS DEFINITIONS */
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#define BMA2x2_STAT1_ADDR 0x09
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#define BMA2x2_STAT2_ADDR 0x0A
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#define BMA2x2_STAT_TAP_SLOPE_ADDR 0x0B
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#define BMA2x2_STAT_ORIENT_HIGH_ADDR 0x0C
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#define BMA2x2_STAT_FIFO_ADDR 0x0E
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#define BMA2x2_RANGE_SELECT_ADDR 0x0F
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#define BMA2x2_RANGE_SELECT_MSK 0x0F
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#define BMA2x2_RANGE_2G 3
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#define BMA2x2_RANGE_4G 5
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#define BMA2x2_RANGE_8G 8
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#define BMA2x2_RANGE_16G 12
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#define BMA2x2_RANGE_TO_REG(_range) \
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((_range) < 8 ? BMA2x2_RANGE_2G + ((_range) / 4) * 2 : \
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BMA2x2_RANGE_8G + ((_range) / 16) * 4)
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#define BMA2x2_REG_TO_RANGE(_reg) \
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((_reg) < BMA2x2_RANGE_8G ? 2 + (_reg) - BMA2x2_RANGE_2G : \
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8 + ((_reg) - BMA2x2_RANGE_8G) * 2)
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#define BMA2x2_BW_SELECT_ADDR 0x10
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#define BMA2x2_BW_MSK 0x1F
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#define BMA2x2_BW_7_81HZ 0x08 /* LowPass 7.81HZ */
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#define BMA2x2_BW_15_63HZ 0x09 /* LowPass 15.63HZ */
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#define BMA2x2_BW_31_25HZ 0x0A /* LowPass 31.25HZ */
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#define BMA2x2_BW_62_50HZ 0x0B /* LowPass 62.50HZ */
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#define BMA2x2_BW_125HZ 0x0C /* LowPass 125HZ */
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#define BMA2x2_BW_250HZ 0x0D /* LowPass 250HZ */
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#define BMA2x2_BW_500HZ 0x0E /* LowPass 500HZ */
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#define BMA2x2_BW_1000HZ 0x0F /* LowPass 1000HZ */
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#define BMA2x2_BW_TO_REG(_bw) \
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((_bw) < 125000 ? BMA2x2_BW_7_81HZ + __fls((_bw) / 7810) : \
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BMA2x2_BW_125HZ + __fls((_bw) / 125000))
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#define BMA2x2_REG_TO_BW(_reg) \
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((_reg) < BMA2x2_BW_125HZ ? 7810 << ((_reg) - BMA2x2_BW_7_81HZ) : \
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125000 << ((_reg) - BMA2x2_BW_125HZ))
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#define BMA2x2_MODE_CTRL_ADDR 0x11
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#define BMA2x2_LOW_NOISE_CTRL_ADDR 0x12
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#define BMA2x2_DATA_CTRL_ADDR 0x13
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#define BMA2x2_RST_ADDR 0x14
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#define BMA2x2_CMD_SOFT_RESET 0xb6
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/* INTERRUPT ADDRESS DEFINITIONS */
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#define BMA2x2_INTR_ENABLE1_ADDR 0x16
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#define BMA2x2_INTR_ENABLE2_ADDR 0x17
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#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR 0x18
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#define BMA2x2_INTR1_PAD_SELECT_ADDR 0x19
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#define BMA2x2_INTR_DATA_SELECT_ADDR 0x1A
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#define BMA2x2_INTR2_PAD_SELECT_ADDR 0x1B
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#define BMA2x2_INTR_SOURCE_ADDR 0x1E
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#define BMA2x2_INTR_SET_ADDR 0x20
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#define BMA2x2_INTR_CTRL_ADDR 0x21
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/* FEATURE ADDRESS DEFINITIONS */
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#define BMA2x2_LOW_DURN_ADDR 0x22
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#define BMA2x2_LOW_THRES_ADDR 0x23
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#define BMA2x2_LOW_HIGH_HYST_ADDR 0x24
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#define BMA2x2_HIGH_DURN_ADDR 0x25
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#define BMA2x2_HIGH_THRES_ADDR 0x26
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#define BMA2x2_SLOPE_DURN_ADDR 0x27
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#define BMA2x2_SLOPE_THRES_ADDR 0x28
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#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR 0x29
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#define BMA2x2_TAP_PARAM_ADDR 0x2A
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#define BMA2x2_TAP_THRES_ADDR 0x2B
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#define BMA2x2_ORIENT_PARAM_ADDR 0x2C
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#define BMA2x2_THETA_BLOCK_ADDR 0x2D
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#define BMA2x2_THETA_FLAT_ADDR 0x2E
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#define BMA2x2_FLAT_HOLD_TIME_ADDR 0x2F
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#define BMA2x2_SELFTEST_ADDR 0x32
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#define BMA2x2_EEPROM_CTRL_ADDR 0x33
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#define BMA2x2_SERIAL_CTRL_ADDR 0x34
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/* OFFSET ADDRESS DEFINITIONS */
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#define BMA2x2_OFFSET_CTRL_ADDR 0x36
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#define BMA2x2_OFFSET_RESET 0x80
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#define BMA2x2_OFFSET_TRIGGER_OFF 5
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#define BMA2x2_OFFSET_TRIGGER_MASK (0x3 << BMA2x2_OFFSET_TRIGGER_OFF)
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#define BMA2x2_OFFSET_CAL_READY 0x10
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#define BMA2x2_OFC_SETTING_ADDR 0x37
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#define BMA2x2_OFC_TARGET_AXIS_OFF 1
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#define BMA2x2_OFC_TARGET_AXIS_LEN 2
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#define BMA2x2_OFC_TARGET_AXIS(_axis) \
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(BMA2x2_OFC_TARGET_AXIS_LEN * (_axis) + BMA2x2_OFC_TARGET_AXIS_OFF)
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#define BMA2x2_OFC_TARGET_0G 0
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#define BMA2x2_OFC_TARGET_PLUS_1G 1
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#define BMA2x2_OFC_TARGET_MINUS_1G 2
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#define BMA2x2_OFFSET_X_AXIS_ADDR 0x38
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#define BMA2x2_OFFSET_Y_AXIS_ADDR 0x39
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#define BMA2x2_OFFSET_Z_AXIS_ADDR 0x3A
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/* GP ADDRESS DEFINITIONS */
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#define BMA2x2_GP0_ADDR 0x3B
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#define BMA2x2_GP1_ADDR 0x3C
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/* FIFO ADDRESS DEFINITIONS */
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#define BMA2x2_FIFO_MODE_ADDR 0x3E
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#define BMA2x2_FIFO_DATA_OUTPUT_ADDR 0x3F
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#define BMA2x2_FIFO_WML_TRIG 0x30
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/* Sensor resolution in number of bits. This sensor has fixed resolution. */
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#define BMA2x2_RESOLUTION 12
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/* Min and Max sampling frequency in mHz */
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#define BMA255_ACCEL_MIN_FREQ 7810
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#define BMA255_ACCEL_MAX_FREQ \
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MOTION_MAX_SENSOR_FREQUENCY(1000000, 15625)
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#endif /* __CROS_EC_ACCEL_BMA2x2_H */
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