238 lines
6.1 KiB
C
238 lines
6.1 KiB
C
/* Copyright 2019 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/*
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* LIS2DW12 accelerometer include file for Chrome EC 3D digital accelerometer.
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* For more details on LIS2DW12 device please refer to www.st.com.
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*/
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#ifndef __CROS_EC_ACCEL_LIS2DW12_H
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#define __CROS_EC_ACCEL_LIS2DW12_H
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#include "driver/stm_mems_common.h"
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/*
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* 7-bit address is 011000Xb. Where 'X' is determined
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* by the voltage on the ADDR pin.
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*/
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#define LIS2DW12_ADDR0 0x18
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#define LIS2DW12_ADDR1 0x19
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#define LIS2DWL_ADDR0_FLAGS 0x18
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#define LIS2DWL_ADDR1_FLAGS 0x19
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#define LIS2DW12_EN_BIT 0x01
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#define LIS2DW12_DIS_BIT 0x00
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/* Who am I. */
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#define LIS2DW12_WHO_AM_I_REG 0x0f
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#define LIS2DW12_WHO_AM_I 0x44
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/* Registers sensor. */
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#define LIS2DW12_CTRL1_ADDR 0x20
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#define LIS2DW12_CTRL2_ADDR 0x21
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#define LIS2DW12_CTRL3_ADDR 0x22
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#define LIS2DW12_CTRL4_ADDR 0x23
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/* CTRL4 bits. */
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#define LIS2DW12_INT1_FTH 0x02
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#define LIS2DW12_INT1_D_TAP 0x08
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#define LIS2DW12_INT1_S_TAP 0x40
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#define LIS2DW12_CTRL5_ADDR 0x24
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/* CTRL5 bits. */
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#define LIS2DW12_INT2_FTH 0x02
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#define LIS2DW12_CTRL6_ADDR 0x25
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#define LIS2DW12_STATUS_REG 0x27
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/* STATUS bits. */
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#define LIS2DW12_STS_DRDY_UP 0x01
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#define LIS2DW12_SINGLE_TAP_UP 0x08
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#define LIS2DW12_DOUBLE_TAP_UP 0x10
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#define LIS2DW12_FIFO_THS_UP 0x80
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#define LIS2DW12_OUT_X_L_ADDR 0x28
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#define LIS2DW12_FIFO_CTRL_ADDR 0x2e
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/* FIFO_CTRL bits. */
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#define LIS2DW12_FIFO_MODE_MASK 0xe0
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/* List of supported FIFO mode. */
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enum lis2dw12_fmode {
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LIS2DW12_FIFO_BYPASS_MODE = 0,
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LIS2DW12_FIFO_MODE,
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LIS2DW12_FIFO_CONT_MODE = 6
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};
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#define LIS2DW12_FIFO_THRESHOLD_MASK 0x1f
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#define LIS2DW12_FIFO_SAMPLES_ADDR 0x2f
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#define LIS2DW12_TAP_THS_X_ADDR 0x30
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#define LIS2DW12_TAP_THS_Y_ADDR 0x31
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#define LIS2DW12_TAP_THS_Z_ADDR 0x32
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#define LIS2DW12_INT_DUR_ADDR 0x33
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#define LIS2DW12_WAKE_UP_THS_ADDR 0x34
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/* TAP bits. */
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#define LIS2DW12_SINGLE_DOUBLE_TAP 0x80
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/* FIFO_SAMPLES bits. */
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#define LIS2DW12_FIFO_DIFF_MASK 0x3f
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#define LIS2DW12_FIFO_OVR_MASK 0x40
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#define LIS2DW12_FIFO_FTH_MASK 0x80
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#define LIS2DW12_ABS_INT_CFG_ADDR 0x3f
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/* INT Configuration bits. */
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#define LIS2DW12_DRDY_PULSED 0x80
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#define LIS2DW12_INT2_ON_INT1 0x40
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#define LIS2DW12_INT_ENABLE 0x20
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/* Alias Registers/Masks. */
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#define LIS2DW12_ACC_ODR_ADDR LIS2DW12_CTRL1_ADDR
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#define LIS2DW12_ACC_ODR_MASK 0xf0
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#define LIS2DW12_ACC_MODE_ADDR LIS2DW12_CTRL1_ADDR
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#define LIS2DW12_ACC_MODE_MASK 0x0c
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/* Power mode selection. */
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enum lis2sw12_mode {
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LIS2DW12_LOW_POWER = 0,
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LIS2DW12_HIGH_PERF,
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LIS2DW12_SINGLE_DC,
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LIS2DW12_LOW_POWER_LIST_NUM
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};
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#define LIS2DW12_ACC_LPMODE_ADDR LIS2DW12_CTRL1_ADDR
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#define LIS2DW12_ACC_LPMODE_MASK 0x03
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/*
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* Low power mode selection.
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* TODO: Support all Low Power Mode. Actually is not supported only
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* LOW_POWER_MODE_1.
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*/
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enum lis2sw12_lpmode {
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LIS2DW12_LOW_POWER_MODE_1 = 0,
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LIS2DW12_LOW_POWER_MODE_2,
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LIS2DW12_LOW_POWER_MODE_3,
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LIS2DW12_LOW_POWER_MODE_4,
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LIS2DW12_LOW_POWER_MODE_LIST_NUM
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};
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#define LIS2DW12_BDU_ADDR LIS2DW12_CTRL2_ADDR
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#define LIS2DW12_BDU_MASK 0x08
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#define LIS2DW12_SOFT_RESET_ADDR LIS2DW12_CTRL2_ADDR
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#define LIS2DW12_SOFT_RESET_MASK 0x40
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#define LIS2DW12_BOOT_ADDR LIS2DW12_CTRL2_ADDR
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#define LIS2DW12_BOOT_MASK 0x80
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#define LIS2DW12_LIR_ADDR LIS2DW12_CTRL3_ADDR
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#define LIS2DW12_LIR_MASK 0x10
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#define LIS2DW12_H_ACTIVE_ADDR LIS2DW12_CTRL3_ADDR
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#define LIS2DW12_H_ACTIVE_MASK 0x08
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#define LIS2DW12_INT1_FTH_ADDR LIS2DW12_CTRL4_ADDR
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#define LIS2DW12_INT1_FTH_MASK LIS2DW12_INT1_FTH
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#define LIS2DW12_INT1_TAP_ADDR LIS2DW12_CTRL4_ADDR
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#define LIS2DW12_INT1_DTAP_MASK 0x08
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#define LIS2DW12_INT1_STAP_MASK 0x40
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#define LIS2DW12_INT1_D_TAP_EN LIS2DW12_INT1_DTAP_MASK
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#define LIS2DW12_STATUS_TAP LIS2DW12_STS_DRDY_UP
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#define LIS2DW12_SINGLE_TAP LIS2DW12_SINGLE_TAP_UP
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#define LIS2DW12_DOUBLE_TAP LIS2DW12_DOUBLE_TAP_UP
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#define LIS2DW12_INT2_ON_INT1_ADDR LIS2DW12_ABS_INT_CFG_ADDR
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#define LIS2DW12_INT2_ON_INT1_MASK LIS2DW12_INT2_ON_INT1
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#define LIS2DW12_DRDY_PULSED_ADDR LIS2DW12_ABS_INT_CFG_ADDR
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#define LIS2DW12_DRDY_PULSED_MASK LIS2DW12_DRDY_PULSED
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/* Acc data rate for HR mode. */
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enum lis2dw12_odr {
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LIS2DW12_ODR_POWER_OFF_VAL = 0x00,
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LIS2DW12_ODR_12HZ_VAL = 0x02,
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LIS2DW12_ODR_25HZ_VAL,
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LIS2DW12_ODR_50HZ_VAL,
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LIS2DW12_ODR_100HZ_VAL,
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LIS2DW12_ODR_200HZ_VAL,
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LIS2DW12_ODR_400HZ_VAL,
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LIS2DW12_ODR_800HZ_VAL,
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LIS2DW12_ODR_1_6kHZ_VAL,
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LIS2DW12_ODR_LIST_NUM
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};
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/* Absolute Acc rate. */
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#define LIS2DW12_ODR_MIN_VAL 12500
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#define LIS2DW12_ODR_MAX_VAL 1600000
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/* ODR reg value from selected data rate in mHz. */
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#define LIS2DW12_ODR_TO_REG(_odr) \
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(__fls(_odr / LIS2DW12_ODR_MIN_VAL) + LIS2DW12_ODR_12HZ_VAL)
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/* Normalized ODR value from selected data rate in mHz. */
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#define LIS2DW12_ODR_TO_NORMALIZE(_odr) \
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(LIS2DW12_ODR_MIN_VAL << (__fls(_odr / LIS2DW12_ODR_MIN_VAL)))
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/* Full scale range registers. */
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#define LIS2DW12_FS_ADDR LIS2DW12_CTRL6_ADDR
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#define LIS2DW12_FS_MASK 0x30
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/* Acc FS value. */
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enum lis2dw12_fs {
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LIS2DW12_FS_2G_VAL = 0x00,
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LIS2DW12_FS_4G_VAL,
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LIS2DW12_FS_8G_VAL,
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LIS2DW12_FS_16G_VAL,
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LIS2DW12_FS_LIST_NUM
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};
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#define LIS2DW12_ACCEL_FS_MAX_VAL 16
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/* Acc Gain value. */
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#define LIS2DW12_FS_2G_GAIN 3904
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#define LIS2DW12_FS_4G_GAIN (LIS2DW12_FS_2G_GAIN << 1)
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#define LIS2DW12_FS_8G_GAIN (LIS2DW12_FS_2G_GAIN << 2)
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#define LIS2DW12_FS_16G_GAIN (LIS2DW12_FS_2G_GAIN << 3)
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/* FS Full Scale value from Gain. */
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#define LIS2DW12_GAIN_FS(_gain) \
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(2 << (31 - __builtin_clz(_gain / LIS2DW12_FS_2G_GAIN)))
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/* Gain value from selected Full Scale. */
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#define LIS2DW12_FS_GAIN(_fs) \
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(LIS2DW12_FS_2G_GAIN << (30 - __builtin_clz(_fs)))
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/* Reg value from Full Scale. */
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#define LIS2DW12_FS_REG(_fs) \
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(30 - __builtin_clz(_fs))
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/* Normalized FS value from Full Scale. */
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#define LIS2DW12_NORMALIZE_FS(_fs) \
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(1 << (30 - __builtin_clz(_fs)))
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/*
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* Sensor resolution in number of bits.
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* Sensor driver support 14 bits resolution.
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* TODO: Support all "LP Power Mode" (res. 12/14 bits).
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*/
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#define LIS2DW12_RESOLUTION 14
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extern const struct accelgyro_drv lis2dw12_drv;
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void lis2dw12_interrupt(enum gpio_signal signal);
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#endif /* __CROS_EC_ACCEL_LIS2DW12_H */
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