107 lines
3.0 KiB
C
107 lines
3.0 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* L3GD20H gyro module for Chrome EC */
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#ifndef __CROS_EC_GYRO_L3GD20H_H
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#define __CROS_EC_GYRO_L3GD20H_H
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#include "accelgyro.h"
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#include "task.h"
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/*
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* 7-bit address is 110101Xb. Where 'X' is determined
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* by the voltage on the ADDR pin.
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*/
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#define L3GD20_ADDR0_FLAGS 0x6a
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#define L3GD20_ADDR1_FLAGS 0x6b
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/* who am I */
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#define L3GD20_WHO_AM_I 0xd7
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/* Chip specific registers. */
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#define L3GD20_WHO_AM_I_REG 0x0f
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#define L3GD20_CTRL_REG1 0x20
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#define L3GD20_CTRL_REG2 0x21
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#define L3GD20_CTRL_REG3 0x22
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#define L3GD20_CTRL_REG4 0x23
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#define L3GD20_CTRL_REG5 0x24
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#define L3GD20_CTRL_REFERENCE 0x25
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#define L3GD20_OUT_TEMP 0x26
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#define L3GD20_STATUS_REG 0x27
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#define L3GD20_OUT_X_L 0x28
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#define L3GD20_OUT_X_H 0x29
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#define L3GD20_OUT_Y_L 0x2a
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#define L3GD20_OUT_Y_H 0x2b
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#define L3GD20_OUT_Z_L 0x2c
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#define L3GD20_OUT_Z_H 0x2d
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#define L3GD20_FIFO_CTRL_REG 0x2e
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#define L3GD20_FIFO_SRC_REG 0x2f
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#define L3GD20_INT1_CFG 0x30
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#define L3GD20_INT1_SRC 0x31
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#define L3GD20_INT1_TSH_XH 0x32
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#define L3GD20_INT1_TSH_XL 0x33
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#define L3GD20_INT1_TSH_YH 0x34
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#define L3GD20_INT1_TSH_YL 0x35
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#define L3GD20_INT1_TSH_ZH 0x36
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#define L3GD20_INT1_TSH_ZL 0x37
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#define L3GD20_INT1_DURATION 0x38
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#define L3GD20_LOW_ODR 0x39
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#define L3GD20_DPS_SEL_245 (0 << 4)
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#define L3GD20_DPS_SEL_500 BIT(4)
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#define L3GD20_DPS_SEL_2000_0 (2 << 4)
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#define L3GD20_DPS_SEL_2000_1 (3 << 4)
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#define L3GD20_ODR_PD (0 << 3)
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#define L3GD20_ODR_12_5HZ (0 << 6)
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#define L3GD20_ODR_25HZ BIT(6)
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#define L3GD20_ODR_50HZ_0 (2 << 6)
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#define L3GD20_ODR_50HZ_1 (3 << 6)
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#define L3GD20_ODR_100HZ (0 << 6)
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#define L3GD20_ODR_200HZ BIT(6)
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#define L3GD20_ODR_400HZ (2 << 6)
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#define L3GD20_ODR_800HZ (3 << 6)
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#define L3GD20_ODR_MASK (3 << 6)
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#define L3GD20_STS_ZYXDA_MASK BIT(3)
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#define L3GD20_RANGE_MASK (3 << 4)
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#define L3GD20_LOW_ODR_MASK BIT(0)
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#define L3GD20_ODR_PD_MASK BIT(3)
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/* Min and Max sampling frequency in mHz */
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#define L3GD20_GYRO_MIN_FREQ 12500
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#define L3GD20_GYRO_MAX_FREQ 800000
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/*
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* Register : STATUS_REG
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* Address : 0X27
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*/
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enum l3gd20_status {
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L3GD20_STS_DOWN = 0x00,
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L3GD20_STS_ZYXDA_UP = 0x08,
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};
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/*
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* Register : CTRL_REG4
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* Address : 0X23
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* Bit Group Name: BDU
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*/
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enum l3gd20_bdu {
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L3GD20_BDU_DISABLE = 0x00,
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L3GD20_BDU_ENABLE = 0x80,
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};
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/* Sensor resolution in number of bits. This sensor has fixed resolution. */
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#define L3GD20_RESOLUTION 16
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extern const struct accelgyro_drv l3gd20h_drv;
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struct l3gd20_data {
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struct accelgyro_saved_data_t base;
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int16_t offset[3];
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};
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#endif /* __CROS_EC_GYRO_L3GD20H_H */
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