555 lines
20 KiB
Ada
555 lines
20 KiB
Ada
--
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-- Copyright (C) 2017 secunet Security Networks AG
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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with GNAT.Source_Info;
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with HW.Debug;
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with HW.GFX.GMA.Config;
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with HW.GFX.GMA.Registers;
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use HW.GFX.GMA.Registers;
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package body HW.GFX.GMA.DDI_Phy is
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subtype Dual_Channel is T range BC .. BC;
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type DDI_Range is record
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First : DDI_Phy_Port;
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Last : DDI_Phy_Port;
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end record;
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type DDI_Range_Array is array (T) of DDI_Range;
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DDIs : constant DDI_Range_Array :=
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(A => (DIGI_A, DIGI_A),
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BC => (DIGI_B, DIGI_C));
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----------------------------------------------------------------------------
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type CL1CM is record
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DW0 : Registers_Index;
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DW9 : Registers_Index;
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DW10 : Registers_Index;
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DW28 : Registers_Index;
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DW30 : Registers_Index;
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end record;
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type CL1CM_Array is array (T) of CL1CM;
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PORT_CL1CM : constant CL1CM_Array :=
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(A =>
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(DW0 => BXT_PORT_CL1CM_DW0_A,
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DW9 => BXT_PORT_CL1CM_DW9_A,
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DW10 => BXT_PORT_CL1CM_DW10_A,
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DW28 => BXT_PORT_CL1CM_DW28_A,
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DW30 => BXT_PORT_CL1CM_DW30_A),
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BC =>
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(DW0 => BXT_PORT_CL1CM_DW0_BC,
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DW9 => BXT_PORT_CL1CM_DW9_BC,
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DW10 => BXT_PORT_CL1CM_DW10_BC,
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DW28 => BXT_PORT_CL1CM_DW28_BC,
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DW30 => BXT_PORT_CL1CM_DW30_BC));
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type CL2CM is record
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DW6 : Registers_Index;
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end record;
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type CL2CM_Array is array (Dual_Channel) of CL2CM;
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PORT_CL2CM : constant CL2CM_Array :=
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(BC => (DW6 => BXT_PORT_CL2CM_DW6_BC));
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type Port_Ref_Regs is record
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DW3 : Registers_Index;
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DW6 : Registers_Index;
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DW8 : Registers_Index;
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end record;
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type Port_Ref_Array is array (T) of Port_Ref_Regs;
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PORT_REF : constant Port_Ref_Array :=
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(A =>
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(DW3 => BXT_PORT_REF_DW3_A,
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DW6 => BXT_PORT_REF_DW6_A,
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DW8 => BXT_PORT_REF_DW8_A),
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BC =>
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(DW3 => BXT_PORT_REF_DW3_BC,
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DW6 => BXT_PORT_REF_DW6_BC,
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DW8 => BXT_PORT_REF_DW8_BC));
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type Regs is array (T) of Registers_Index;
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PHY_CTL_FAMILY : constant Regs :=
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(A => BXT_PHY_CTL_FAM_EDP, BC => BXT_PHY_CTL_FAM_DDI);
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type DDI_Regs is array (DDI_Phy_Port) of Registers_Index;
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PHY_CTL : constant DDI_Regs :=
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(DIGI_A => BXT_PHY_CTL_A,
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DIGI_B => BXT_PHY_CTL_B,
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DIGI_C => BXT_PHY_CTL_C);
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----------------------------------------------------------------------------
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type Values is array (T) of Word32;
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GT_DISPLAY_POWER_ON : constant Values :=
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(A => 1 * 2 ** 1,
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BC => 1 * 2 ** 0);
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PORT_CL1CM_PHY_POWER_GOOD : constant := 1 * 2 ** 16;
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PORT_CL1CM_PHY_RESERVED : constant := 1 * 2 ** 7;
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PORT_CL1CM_IREFxRC_OFFSET_SHIFT : constant := 8;
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PORT_CL1CM_IREFxRC_OFFSET_MASK : constant := 16#ff# * 2 ** 8;
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PORT_CL1CM_OCL1_POWER_DOWN_EN : constant := 1 * 2 ** 23;
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PORT_CL1CM_OLDO_DYN_POWER_DOWN_EN : constant := 1 * 2 ** 22;
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PORT_CL1CM_SUS_CLK_CONFIG : constant := 3 * 2 ** 0;
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PORT_CL2CM_OLDO_DYN_POWER_DOWN_EN : constant := 1 * 2 ** 28;
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PORT_REF_GRC_DONE : constant := 1 * 2 ** 22;
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PORT_REF_GRC_CODE_SHIFT : constant := 24;
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PORT_REF_GRC_FAST_SHIFT : constant := 16;
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PORT_REF_GRC_SLOW_SHIFT : constant := 8;
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PORT_REF_GRC_DISABLE : constant := 1 * 2 ** 15;
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PORT_REF_GRC_READY_OVERRIDE : constant := 1 * 2 ** 1;
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PHY_CTL_FAM_CMN_RESET_DIS : constant := 1 * 2 ** 31;
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PHY_CTL_CMNLANE_POWERDOWN_ACK : constant := 1 * 2 ** 10;
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----------------------------------------------------------------------------
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procedure Is_Enabled (Phy : in T; Enabled : out Boolean)
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is
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Phy_Pwr : Word32;
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Is_Set_Mask (BXT_P_CR_GT_DISP_PWRON, GT_DISPLAY_POWER_ON (Phy), Enabled);
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if Enabled then
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Read (PORT_CL1CM (Phy).DW0, Phy_Pwr);
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Enabled :=
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(Phy_Pwr and (PORT_CL1CM_PHY_POWER_GOOD or PORT_CL1CM_PHY_RESERVED))
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= PORT_CL1CM_PHY_POWER_GOOD;
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pragma Debug (not Enabled, Debug.Put_Line ("DDI PHY power unsettled"));
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end if;
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if Enabled then
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Is_Set_Mask (PHY_CTL_FAMILY (Phy), PHY_CTL_FAM_CMN_RESET_DIS, Enabled);
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pragma Debug (not Enabled, Debug.Put_Line ("DDI PHY still in reset"));
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end if;
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for DDI in DDIs (Phy).First .. DDIs (Phy).Last loop
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if Enabled then
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declare
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Common_Lane_Powerdown : Boolean;
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begin
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Is_Set_Mask
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(Register => PHY_CTL (DDI),
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Mask => PHY_CTL_CMNLANE_POWERDOWN_ACK,
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Result => Common_Lane_Powerdown);
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Enabled := not Common_Lane_Powerdown;
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pragma Debug
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(not Enabled, Debug.Put_Line ("Common lane powered down"));
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end;
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end if;
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end loop;
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end Is_Enabled;
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procedure Power_On_Phy (Phy : T)
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with
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Pre => True
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is
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Set_Mask (BXT_P_CR_GT_DISP_PWRON, GT_DISPLAY_POWER_ON (Phy));
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Wait
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(Register => PORT_CL1CM (Phy).DW0,
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Mask => PORT_CL1CM_PHY_POWER_GOOD or
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PORT_CL1CM_PHY_RESERVED,
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Value => PORT_CL1CM_PHY_POWER_GOOD,
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TOut_MS => 1); -- 50~100us
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Unset_And_Set_Mask
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(Register => PORT_CL1CM (Phy).DW9,
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Mask_Unset => PORT_CL1CM_IREFxRC_OFFSET_MASK,
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Mask_Set => Shift_Left
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(16#e4#, PORT_CL1CM_IREFxRC_OFFSET_SHIFT));
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Unset_And_Set_Mask
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(Register => PORT_CL1CM (Phy).DW10,
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Mask_Unset => PORT_CL1CM_IREFxRC_OFFSET_MASK,
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Mask_Set => Shift_Left
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(16#e4#, PORT_CL1CM_IREFxRC_OFFSET_SHIFT));
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Set_Mask
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(Register => PORT_CL1CM (Phy).DW28,
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Mask => PORT_CL1CM_OCL1_POWER_DOWN_EN or
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PORT_CL1CM_OLDO_DYN_POWER_DOWN_EN or
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PORT_CL1CM_SUS_CLK_CONFIG);
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if Phy in Dual_Channel then
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Set_Mask (PORT_CL2CM (Phy).DW6, PORT_CL2CM_OLDO_DYN_POWER_DOWN_EN);
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end if;
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if Phy = BC then
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declare
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GRC_Val : Word32;
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begin
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-- take RCOMP calibration result from A
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Wait_Set_Mask (PORT_REF (A).DW3, PORT_REF_GRC_DONE, TOut_MS => 10);
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Read (PORT_REF (A).DW6, GRC_Val);
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GRC_Val := Shift_Right (GRC_Val, PORT_REF_GRC_CODE_SHIFT);
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-- use it for BC too
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GRC_Val := Shift_Left (GRC_Val, PORT_REF_GRC_FAST_SHIFT) or
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Shift_Left (GRC_Val, PORT_REF_GRC_SLOW_SHIFT) or
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GRC_Val;
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Write (PORT_REF (Phy).DW6, GRC_Val);
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Set_Mask
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(Register => PORT_REF (Phy).DW8,
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Mask => PORT_REF_GRC_DISABLE or
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PORT_REF_GRC_READY_OVERRIDE);
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end;
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end if;
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Set_Mask (PHY_CTL_FAMILY (Phy), PHY_CTL_FAM_CMN_RESET_DIS);
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end Power_On_Phy;
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procedure Power_On (Phy : T)
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is
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Phy_A_Enabled : Boolean := False;
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Enabled : Boolean;
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Is_Enabled (Phy, Enabled);
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pragma Debug (Enabled, Debug.Put_Line ("DDI PHY already enabled"));
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if not Enabled then
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if Phy = BC then
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-- PHY BC needs RCOMP calibration results from PHY A
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Is_Enabled (A, Phy_A_Enabled);
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if not Phy_A_Enabled then
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Power_On_Phy (A);
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end if;
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end if;
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Power_On_Phy (Phy);
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if Phy = BC and then not Phy_A_Enabled then
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Power_Off (A);
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end if;
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end if;
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end Power_On;
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procedure Power_Off (Phy : T) is
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Unset_Mask (PHY_CTL_FAMILY (Phy), PHY_CTL_FAM_CMN_RESET_DIS);
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Unset_Mask (BXT_P_CR_GT_DISP_PWRON, GT_DISPLAY_POWER_ON (Phy));
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end Power_Off;
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----------------------------------------------------------------------------
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type Lanes is range 0 .. 3;
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type Lane_Reg_Array is array (Lanes) of Registers_Index;
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type Port_TX_Regs is record
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DW2_LN0 : Registers_Index;
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DW2_GRP : Registers_Index;
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DW3_LN0 : Registers_Index;
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DW3_GRP : Registers_Index;
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DW4_LN0 : Registers_Index;
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DW4_GRP : Registers_Index;
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DW14_LN : Lane_Reg_Array;
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end record;
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type Port_TX_Array is array (DDI_Phy_Port) of Port_TX_Regs;
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PORT_TX : constant Port_TX_Array :=
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(DIGI_A =>
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(DW2_LN0 => BXT_PORT_TX_DW2_LN0_A,
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DW2_GRP => BXT_PORT_TX_DW2_GRP_A,
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DW3_LN0 => BXT_PORT_TX_DW3_LN0_A,
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DW3_GRP => BXT_PORT_TX_DW3_GRP_A,
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DW4_LN0 => BXT_PORT_TX_DW4_LN0_A,
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DW4_GRP => BXT_PORT_TX_DW4_GRP_A,
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DW14_LN =>
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(BXT_PORT_TX_DW14_LN0_A,
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BXT_PORT_TX_DW14_LN1_A,
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BXT_PORT_TX_DW14_LN2_A,
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BXT_PORT_TX_DW14_LN3_A)),
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DIGI_B =>
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(DW2_LN0 => BXT_PORT_TX_DW2_LN0_B,
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DW2_GRP => BXT_PORT_TX_DW2_GRP_B,
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DW3_LN0 => BXT_PORT_TX_DW3_LN0_B,
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DW3_GRP => BXT_PORT_TX_DW3_GRP_B,
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DW4_LN0 => BXT_PORT_TX_DW4_LN0_B,
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DW4_GRP => BXT_PORT_TX_DW4_GRP_B,
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DW14_LN =>
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(BXT_PORT_TX_DW14_LN0_B,
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BXT_PORT_TX_DW14_LN1_B,
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BXT_PORT_TX_DW14_LN2_B,
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BXT_PORT_TX_DW14_LN3_B)),
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DIGI_C =>
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(DW2_LN0 => BXT_PORT_TX_DW2_LN0_C,
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DW2_GRP => BXT_PORT_TX_DW2_GRP_C,
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DW3_LN0 => BXT_PORT_TX_DW3_LN0_C,
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DW3_GRP => BXT_PORT_TX_DW3_GRP_C,
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DW4_LN0 => BXT_PORT_TX_DW4_LN0_C,
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DW4_GRP => BXT_PORT_TX_DW4_GRP_C,
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DW14_LN =>
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(BXT_PORT_TX_DW14_LN0_C,
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BXT_PORT_TX_DW14_LN1_C,
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BXT_PORT_TX_DW14_LN2_C,
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BXT_PORT_TX_DW14_LN3_C)));
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PORT_TX_DW2_MARGIN_000_SHIFT : constant := 16;
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PORT_TX_DW2_MARGIN_000_MASK : constant := 16#ff# * 2 ** 16;
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PORT_TX_DW2_UNIQ_TRANS_SCALE_SHIFT : constant := 8;
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PORT_TX_DW2_UNIQ_TRANS_SCALE_MASK : constant := 16#ff# * 2 ** 8;
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function PORT_TX_DW2_MARGIN_000 (Margin : Word8) return Word32 is
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begin
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return Shift_Left (Word32 (Margin), PORT_TX_DW2_MARGIN_000_SHIFT);
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end PORT_TX_DW2_MARGIN_000;
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function PORT_TX_DW2_UNIQ_TRANS_SCALE (Scale : Word8) return Word32 is
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begin
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return Shift_Left (Word32 (Scale), PORT_TX_DW2_UNIQ_TRANS_SCALE_SHIFT);
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end PORT_TX_DW2_UNIQ_TRANS_SCALE;
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PORT_TX_DW3_UNIQUE_TRANGE_EN_METHOD : constant := 1 * 2 ** 27;
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PORT_TX_DW3_SCALE_DCOMP_METHOD : constant := 1 * 2 ** 26;
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PORT_TX_DW4_DE_EMPHASIS_SHIFT : constant := 24;
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PORT_TX_DW4_DE_EMPHASIS_MASK : constant := 16#ff# * 2 ** 24;
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function PORT_TX_DW4_DE_EMPHASIS (De_Emph : Word8) return Word32 is
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begin
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return Shift_Left (Word32 (De_Emph), PORT_TX_DW4_DE_EMPHASIS_SHIFT);
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end PORT_TX_DW4_DE_EMPHASIS;
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PORT_TX_DW14_LN_LATENCY_OPTIM : constant := 1 * 2 ** 30;
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----------------------------------------------------------------------------
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type Port_PCS_Regs is record
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DW10_LN01 : Registers_Index;
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DW10_GRP : Registers_Index;
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end record;
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type Port_PCS_Array is array (DDI_Phy_Port) of Port_PCS_Regs;
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PORT_PCS : constant Port_PCS_Array :=
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(DIGI_A =>
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(DW10_LN01 => BXT_PORT_PCS_DW10_01_A,
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DW10_GRP => BXT_PORT_PCS_DW10_GRP_A),
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DIGI_B =>
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(DW10_LN01 => BXT_PORT_PCS_DW10_01_B,
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DW10_GRP => BXT_PORT_PCS_DW10_GRP_B),
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DIGI_C =>
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(DW10_LN01 => BXT_PORT_PCS_DW10_01_C,
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DW10_GRP => BXT_PORT_PCS_DW10_GRP_C));
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PORT_PCS_TX2_SWING_CALC_INIT : constant := 1 * 2 ** 31;
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PORT_PCS_TX1_SWING_CALC_INIT : constant := 1 * 2 ** 30;
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----------------------------------------------------------------------------
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procedure Pre_PLL (Port_Cfg : Port_Config)
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is
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type Lane_Values is array (Lanes) of Word32;
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Lane_Optim : constant Lane_Values :=
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(if Port_Cfg.Display = HDMI or
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Port_Cfg.DP.Lane_Count = DP_Lane_Count_4
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then
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(0 => PORT_TX_DW14_LN_LATENCY_OPTIM,
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1 => 0,
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2 => PORT_TX_DW14_LN_LATENCY_OPTIM,
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3 => PORT_TX_DW14_LN_LATENCY_OPTIM)
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elsif Port_Cfg.DP.Lane_Count = DP_Lane_Count_2 then
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(0 => PORT_TX_DW14_LN_LATENCY_OPTIM,
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1 => 0,
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2 => PORT_TX_DW14_LN_LATENCY_OPTIM,
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3 => 0)
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else
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(Lanes => 0));
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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if Port_Cfg.Port in DDI_Phy_Port then
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for Lane in Lanes loop
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Unset_And_Set_Mask
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(Register => PORT_TX (Port_Cfg.Port).DW14_LN (Lane),
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Mask_Unset => PORT_TX_DW14_LN_LATENCY_OPTIM,
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Mask_Set => Lane_Optim (Lane));
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end loop;
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end if;
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end Pre_PLL;
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----------------------------------------------------------------------------
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type DDI_Buf_Trans is record
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Margin : Word8;
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Scale : Word8;
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Scale_En : Boolean;
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De_Emph : Word8;
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end record;
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Invalid_Buf_Trans : constant DDI_Buf_Trans := (0, 0, False, 0);
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function DP_Buf_Trans (TS : DP_Info.Train_Set) return DDI_Buf_Trans
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with
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Pre => True
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is
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begin
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return
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(case TS.Voltage_Swing is
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when DP_Info.VS_Level_0 =>
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(case TS.Pre_Emph is
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when DP_Info.Emph_Level_0 => ( 52, 16#9a#, False, 128),
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when DP_Info.Emph_Level_1 => ( 78, 16#9a#, False, 85),
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when DP_Info.Emph_Level_2 => (104, 16#9a#, False, 64),
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when DP_Info.Emph_Level_3 => (154, 16#9a#, False, 43)),
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when DP_Info.VS_Level_1 =>
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(case TS.Pre_Emph is
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when DP_Info.Emph_Level_0 => ( 77, 16#9a#, False, 128),
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when DP_Info.Emph_Level_1 => (116, 16#9a#, False, 85),
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when DP_Info.Emph_Level_2 => (154, 16#9a#, False, 64),
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when others => Invalid_Buf_Trans),
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when DP_Info.VS_Level_2 =>
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(case TS.Pre_Emph is
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when DP_Info.Emph_Level_0 => (102, 16#9a#, False, 128),
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when DP_Info.Emph_Level_1 => (154, 16#9a#, False, 85),
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when others => Invalid_Buf_Trans),
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when DP_Info.VS_Level_3 =>
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(case TS.Pre_Emph is
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when DP_Info.Emph_Level_0 => (154, 16#9a#, True, 128),
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when others => Invalid_Buf_Trans));
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end DP_Buf_Trans;
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function eDP_Buf_Trans (TS : DP_Info.Train_Set) return DDI_Buf_Trans
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|
with
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|
Pre => True
|
|
is
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|
begin
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|
return
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|
(case TS.Voltage_Swing is
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|
when DP_Info.VS_Level_0 =>
|
|
(case TS.Pre_Emph is
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|
when DP_Info.Emph_Level_0 => ( 26, 16#00#, False, 128),
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|
when DP_Info.Emph_Level_1 => ( 38, 16#00#, False, 112),
|
|
when DP_Info.Emph_Level_2 => ( 48, 16#00#, False, 96),
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|
when DP_Info.Emph_Level_3 => ( 54, 16#00#, False, 69)),
|
|
when DP_Info.VS_Level_1 =>
|
|
(case TS.Pre_Emph is
|
|
when DP_Info.Emph_Level_0 => ( 32, 16#00#, False, 128),
|
|
when DP_Info.Emph_Level_1 => ( 48, 16#00#, False, 104),
|
|
when DP_Info.Emph_Level_2 => ( 54, 16#00#, False, 85),
|
|
when others => Invalid_Buf_Trans),
|
|
when DP_Info.VS_Level_2 =>
|
|
(case TS.Pre_Emph is
|
|
when DP_Info.Emph_Level_0 => ( 43, 16#00#, False, 128),
|
|
when DP_Info.Emph_Level_1 => ( 54, 16#00#, False, 101),
|
|
when others => Invalid_Buf_Trans),
|
|
when DP_Info.VS_Level_3 =>
|
|
(case TS.Pre_Emph is
|
|
when DP_Info.Emph_Level_0 => ( 48, 16#00#, False, 128),
|
|
when others => Invalid_Buf_Trans));
|
|
end eDP_Buf_Trans;
|
|
|
|
type HDMI_Buf_Trans_Array is array (HDMI_Buf_Trans_Range) of DDI_Buf_Trans;
|
|
HDMI_Buf_Trans : constant HDMI_Buf_Trans_Array :=
|
|
(0 => ( 52, 16#9a#, False, 128),
|
|
1 => ( 52, 16#9a#, False, 85),
|
|
2 => ( 52, 16#9a#, False, 64),
|
|
3 => ( 42, 16#9a#, False, 43), -- XXX: typo in i915?
|
|
4 => ( 77, 16#9a#, False, 128),
|
|
5 => ( 77, 16#9a#, False, 85),
|
|
6 => ( 77, 16#9a#, False, 64),
|
|
7 => (102, 16#9a#, False, 128),
|
|
8 => (102, 16#9a#, False, 85),
|
|
9 => (154, 16#9a#, True, 128));
|
|
|
|
procedure Set_Signal_Levels
|
|
(Port : DDI_Phy_Port;
|
|
Trans : DDI_Buf_Trans)
|
|
with
|
|
Pre => True
|
|
is
|
|
-- We read from / write to different registers
|
|
-- to program all lanes in a group at once.
|
|
Val32 : Word32;
|
|
begin
|
|
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
|
|
|
|
Read (PORT_PCS (Port).DW10_LN01, Val32);
|
|
Val32 := Val32 and
|
|
not PORT_PCS_TX2_SWING_CALC_INIT and
|
|
not PORT_PCS_TX1_SWING_CALC_INIT;
|
|
Write (PORT_PCS (Port).DW10_GRP, Val32);
|
|
|
|
Read (PORT_TX (Port).DW2_LN0, Val32);
|
|
Val32 := Val32 and
|
|
not PORT_TX_DW2_MARGIN_000_MASK and
|
|
not PORT_TX_DW2_UNIQ_TRANS_SCALE_MASK;
|
|
Val32 := Val32 or
|
|
PORT_TX_DW2_MARGIN_000 (Trans.Margin) or
|
|
PORT_TX_DW2_UNIQ_TRANS_SCALE (Trans.Scale);
|
|
Write (PORT_TX (Port).DW2_GRP, Val32);
|
|
|
|
Read (PORT_TX (Port).DW3_LN0, Val32);
|
|
Val32 := Val32 and not PORT_TX_DW3_SCALE_DCOMP_METHOD;
|
|
if Trans.Scale_En then
|
|
Val32 := Val32 or PORT_TX_DW3_SCALE_DCOMP_METHOD;
|
|
end if;
|
|
Write (PORT_TX (Port).DW3_GRP, Val32);
|
|
|
|
pragma Debug
|
|
((Val32 and PORT_TX_DW3_UNIQUE_TRANGE_EN_METHOD) /= 0 and
|
|
(Val32 and PORT_TX_DW3_SCALE_DCOMP_METHOD) = 0,
|
|
Debug.Put_Line ("XXX: Unique trange enabled but scaling disabled."));
|
|
|
|
Read (PORT_TX (Port).DW4_LN0, Val32);
|
|
Val32 := Val32 and not PORT_TX_DW4_DE_EMPHASIS_MASK;
|
|
Val32 := Val32 or PORT_TX_DW4_DE_EMPHASIS (Trans.De_Emph);
|
|
Write (PORT_TX (Port).DW4_GRP, Val32);
|
|
|
|
Read (PORT_PCS (Port).DW10_LN01, Val32);
|
|
Val32 := Val32 or
|
|
PORT_PCS_TX2_SWING_CALC_INIT or
|
|
PORT_PCS_TX1_SWING_CALC_INIT;
|
|
Write (PORT_PCS (Port).DW10_GRP, Val32);
|
|
end Set_Signal_Levels;
|
|
|
|
procedure Set_DP_Signal_Levels
|
|
(Port : Digital_Port;
|
|
Train_Set : DP_Info.Train_Set)
|
|
is
|
|
Trans : constant DDI_Buf_Trans :=
|
|
(if Port = DIGI_A and Config.EDP_Low_Voltage_Swing then
|
|
eDP_Buf_Trans (Train_Set)
|
|
else
|
|
DP_Buf_Trans (Train_Set));
|
|
begin
|
|
if Port in DDI_Phy_Port then
|
|
Set_Signal_Levels (Port, Trans);
|
|
end if;
|
|
end Set_DP_Signal_Levels;
|
|
|
|
procedure Set_HDMI_Signal_Levels
|
|
(Port : DDI_Phy_Port;
|
|
Level : HDMI_Buf_Trans_Range)
|
|
is
|
|
begin
|
|
Set_Signal_Levels (Port, HDMI_Buf_Trans (Level));
|
|
end Set_HDMI_Signal_Levels;
|
|
|
|
end HW.GFX.GMA.DDI_Phy;
|