118 lines
4.5 KiB
ArmAsm
118 lines
4.5 KiB
ArmAsm
/*
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* Optimized assembly for low-level CPU operations on ARMv7 processors.
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*
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* Cache flushing code based off sys/arch/arm/arm/cpufunc_asm_armv7.S in NetBSD
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*
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* Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
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* Copyright (c) 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <arch/asm.h>
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/*
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* Dcache invalidations by set/way work by passing a [way:sbz:set:sbz:level:0]
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* bitfield in a register to the appropriate MCR instruction. This algorithm
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* works by initializing a bitfield with the highest-numbered set and way, and
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* generating a "set decrement" and a "way decrement". The former just contains
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* the LSB of the set field, but the latter contains the LSB of the way field
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* minus the highest valid set field... such that when you subtract it from a
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* [way:0:level] field you end up with a [way - 1:highest_set:level] field
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* through the magic of double subtraction. It's quite ingenius, really.
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* Takes care to only use r0-r3 and ip so it's pefectly ABI-compatible without
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* needing to write to memory.
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*/
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.macro dcache_apply_all crm
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dsb
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mov r3, #-2 @ initialize level so that we start at 0
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1: @next_level
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add r3, r3, #2 @ increment level
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mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
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and ip, r0, #0x07000000 @ narrow to LoC
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lsr ip, ip, #23 @ left align LoC (low 4 bits)
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cmp r3, ip @ compare
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bge 3f @done @ else fall through (r0 == CLIDR)
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add r2, r3, r3, lsr #1 @ r2 = (level << 1) * 3 / 2
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mov r1, r0, lsr r2 @ r1 = cache type
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and r1, r1, #7
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cmp r1, #2 @ is it data or i&d?
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blt 1b @next_level @ nope, skip level
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mcr p15, 2, r3, c0, c0, 0 @ select cache level
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isb
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mrc p15, 1, r0, c0, c0, 0 @ read CCSIDR
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ubfx ip, r0, #0, #3 @ get linesize from CCSIDR
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add ip, ip, #4 @ apply bias
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ubfx r2, r0, #13, #15 @ get numsets - 1 from CCSIDR
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lsl r2, r2, ip @ shift to set position
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orr r3, r3, r2 @ merge set into way/set/level
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mov r1, #1
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lsl r1, r1, ip @ r1 = set decr
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ubfx ip, r0, #3, #10 @ get numways - 1 from [to be discarded] CCSIDR
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clz r2, ip @ number of bits to MSB of way
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lsl ip, ip, r2 @ shift by that into way position
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mov r0, #1
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lsl r2, r0, r2 @ r2 now contains the way decr
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mov r0, r3 @ get sets/level (no way yet)
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orr r3, r3, ip @ merge way into way/set/level
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bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1
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sub r2, r2, r0 @ subtract from way decr
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/* r3 = ways/sets/level, r2 = way decr, r1 = set decr, r0 and ip are free */
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2: mcr p15, 0, r3, c7, \crm, 2 @ writeback and/or invalidate line
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cmp r3, #15 @ are we done with this level (way/set == 0)
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bls 1b @next_level @ yes, go to next level
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lsr r0, r3, #4 @ clear level bits leaving only way/set bits
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lsls r0, r0, #14 @ clear way bits leaving only set bits
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subne r3, r3, r1 @ non-zero?, decrement set #
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subeq r3, r3, r2 @ zero?, decrement way # and restore set count
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b 2b
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3: @done
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mov r0, #0 @ default back to cache level 0
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mcr p15, 2, r0, c0, c0, 0 @ select cache level
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dsb
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isb
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bx lr
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.endm
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ENTRY(dcache_invalidate_all)
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dcache_apply_all crm=c6
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ENDPROC(dcache_invalidate_all)
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ENTRY(dcache_clean_all)
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dcache_apply_all crm=c10
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ENDPROC(dcache_clean_all)
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ENTRY(dcache_clean_invalidate_all)
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dcache_apply_all crm=c14
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ENDPROC(dcache_clean_invalidate_all)
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