121 lines
4.4 KiB
C
121 lines
4.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* cache.h: Cache maintenance API for ARM64
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*/
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#ifndef ARM64_CACHE_H
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#define ARM64_CACHE_H
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#include <stddef.h>
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#include <stdint.h>
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/* SCTLR bits */
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#define SCTLR_M (1 << 0) /* MMU enable */
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#define SCTLR_A (1 << 1) /* Alignment check enable */
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#define SCTLR_C (1 << 2) /* Data/unified cache enable */
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/* Bits 4:3 are reserved */
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#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */
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/* Bit 6 is reserved */
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#define SCTLR_B (1 << 7) /* Endianness */
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/* Bits 9:8 */
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#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */
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#define SCTLR_Z (1 << 11) /* Branch prediction enable */
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#define SCTLR_I (1 << 12) /* Instruction cache enable */
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#define SCTLR_V (1 << 13) /* Low/high exception vectors */
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#define SCTLR_RR (1 << 14) /* Round Robin select */
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/* Bits 16:15 are reserved */
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#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */
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/* Bit 18 is reserved */
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/* Bits 20:19 reserved virtualization not supported */
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#define SCTLR_WXN (1 << 19) /* Write permission implies XN */
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#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission
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implies PL1 XN */
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#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */
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#define SCTLR_U (1 << 22) /* Unaligned access behavior */
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#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */
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#define SCTLR_EE (1 << 25) /* Exception endianness */
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/* Bit 26 is reserved */
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#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */
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#define SCTLR_TRE (1 << 28) /* TEX remap enable */
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#define SCTLR_AFE (1 << 29) /* Access flag enable */
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#define SCTLR_TE (1 << 30) /* Thumb exception enable */
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/* Bit 31 is reserved */
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/*
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* Cache maintenance API
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*/
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/* dcache clean and invalidate all (on current level given by CCSELR) */
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void dcache_clean_invalidate_all(void);
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/* dcache clean by virtual address to PoC */
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void dcache_clean_by_mva(void const *addr, size_t len);
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/* dcache clean and invalidate by virtual address to PoC */
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void dcache_clean_invalidate_by_mva(void const *addr, size_t len);
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/* dcache invalidate by virtual address to PoC */
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void dcache_invalidate_by_mva(void const *addr, size_t len);
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void dcache_clean_all(void);
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/* dcache invalidate all (on current level given by CCSELR) */
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void dcache_invalidate_all(void);
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/* returns number of bytes per cache line */
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unsigned int dcache_line_bytes(void);
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/* dcache and MMU disable */
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void dcache_mmu_disable(void);
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/* dcache and MMU enable */
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void dcache_mmu_enable(void);
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/* perform all icache/dcache maintenance needed after loading new code */
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void cache_sync_instructions(void);
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/* Ensure that loaded program segment is synced back from cache to PoC */
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void arch_program_segment_loaded(void const *addr, size_t len);
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/* tlb invalidate all */
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void tlb_invalidate_all(void);
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/* Invalidate all of the instruction cache for PE to PoU. */
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static inline void icache_invalidate_all(void)
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{
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__asm__ __volatile__(
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"dsb sy\n\t"
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"ic iallu\n\t"
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"dsb sy\n\t"
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"isb\n\t"
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: : : "memory");
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}
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#endif /* ARM64_CACHE_H */
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