159 lines
4.2 KiB
Plaintext
159 lines
4.2 KiB
Plaintext
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USB
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coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting...
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running main(bist = 0)
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WARNING: Ignoring S4-assertion-width violation.
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Stepping B3
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2 CPU cores
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AMT enabled
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capable of DDR2 of 800 MHz or lower
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VT-d enabled
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GMCH: GS45, using high performance mode by default
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TXT enabled
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Render frequency: 533 MHz
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IGD enabled
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PCIe-to-GMCH enabled
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GMCH supports DDR3 with 1067 MT or less
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GMCH supports FSB with up to 1067 MHz
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SMBus controller enabled.
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0:50:ff
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2:51:b
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DDR mask 4, DDR 3
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Bank 1 populated:
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Raw card type: B
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Row addr bits: 15
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Col addr bits: 10
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byte width: 1
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page size: 1024
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banks: 8
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ranks: 1
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tAAmin: 105
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tCKmin: 12
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Max clock: 666 MHz
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CAS: 0x07e0
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DIMMs support 666 MHz, but chipset only runs at up to 533. Limiting...
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Trying CAS 7, tCK 15.
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Found compatible clock / CAS pair: 533 / 7.
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Timing values:
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tCLK: 15
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tRAS: 20
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tRP: 7
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tRCD: 7
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tRFC: 104
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tWR: 8
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tRD: 11
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tRRD: 4
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tFAW: 20
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tWL: 6
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Changing memory frequency: old 3, new 6.
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Setting IGD memory frequencies for VCO #1.
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Memory configured in single-channel mode.
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Memory map:
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TOM = 128MB
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TOLUD = 128MB
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TOUUD = 128MB
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REMAP: base = 65535MB
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limit = 0MB
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usedMEsize: 0MB
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Performing Jedec initialization at address 0x00000000.
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Final timings for group 0 on channel 1: 6.0.2.6.4
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Final timings for group 1 on channel 1: 6.0.2.6.4
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Final timings for group 2 on channel 1: 6.0.2.8.3
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Final timings for group 3 on channel 1: 6.0.2.8.6
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Lower bound for byte lane 0 on channel 1: 0.0
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Upper bound for byte lane 0 on channel 1: 10.4
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Final timings for byte lane 0 on channel 1: 5.2
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Lower bound for byte lane 1 on channel 1: 0.0
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Upper bound for byte lane 1 on channel 1: 11.2
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Final timings for byte lane 1 on channel 1: 5.5
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Lower bound for byte lane 2 on channel 1: 0.0
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Upper bound for byte lane 2 on channel 1: 10.5
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Final timings for byte lane 2 on channel 1: 5.2
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Lower bound for byte lane 3 on channel 1: 0.0
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Upper bound for byte lane 3 on channel 1: 9.7
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Final timings for byte lane 3 on channel 1: 4.7
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Timing overflow during read training.
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Read training failure: lower bound.
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USB
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coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting...
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running main(bist = 0)
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Interrupted RAM init, reset required.
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USB
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coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting...
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running main(bist = 0)
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Stepping B3
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2 CPU cores
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AMT enabled
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capable of DDR2 of 800 MHz or lower
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VT-d enabled
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GMCH: GS45, using high performance mode by default
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TXT enabled
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Render frequency: 533 MHz
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IGD enabled
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PCIe-to-GMCH enabled
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GMCH supports DDR3 with 1067 MT or less
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GMCH supports FSB with up to 1067 MHz
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SMBus controller enabled.
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0:50:ff
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2:51:b
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DDR mask 4, DDR 3
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Bank 1 populated:
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Raw card type: B
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Row addr bits: 15
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Col addr bits: 10
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byte width: 1
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page size: 1024
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banks: 8
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ranks: 1
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tAAmin: 105
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tCKmin: 12
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Max clock: 666 MHz
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CAS: 0x07e0
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DIMMs support 666 MHz, but chipset only runs at up to 533. Limiting...
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Trying CAS 7, tCK 15.
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Found compatible clock / CAS pair: 533 / 7.
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Timing values:
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tCLK: 15
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tRAS: 20
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tRP: 7
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tRCD: 7
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tRFC: 104
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tWR: 8
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tRD: 11
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tRRD: 4
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tFAW: 20
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tWL: 6
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Setting IGD memory frequencies for VCO #1.
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Memory configured in single-channel mode.
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Memory map:
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TOM = 128MB
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TOLUD = 128MB
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TOUUD = 128MB
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REMAP: base = 65535MB
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limit = 0MB
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usedMEsize: 0MB
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Performing Jedec initialization at address 0x00000000.
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Final timings for group 0 on channel 1: 6.0.2.7.6
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Final timings for group 1 on channel 1: 6.0.2.6.6
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Final timings for group 2 on channel 1: 6.0.2.8.7
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Final timings for group 3 on channel 1: 6.1.0.2.5
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Lower bound for byte lane 0 on channel 1: 0.0
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Upper bound for byte lane 0 on channel 1: 10.3
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Final timings for byte lane 0 on channel 1: 5.1
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Lower bound for byte lane 1 on channel 1: 0.0
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Upper bound for byte lane 1 on channel 1: 11.3
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Final timings for byte lane 1 on channel 1: 5.5
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Lower bound for byte lane 2 on channel 1: 0.0
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Upper bound for byte lane 2 on channel 1: 10.5
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Final timings for byte lane 2 on channel 1: 5.2
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Lower bound for byte lane 3 on channel 1: 0.0
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Upper bound for byte lane 3 on channel 1: 9.6
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Final timings for byte lane 3 on channel 1: 4.7
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Timing overflow during read training.
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Read training failure: lower bound.
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