9938fa14b1
Coreboot is enabling PECI on these CPUs which, according to Intel erratum, must only be done after loading microcode updates, otherwise the CPUID feature set becomes corrupted. That's my understanding, and I think this is why SpeedStep is broken. To be specific, it could but but operating systems no longer detect that the feature is supported. In any case, belgin on IRC found the commit in coreboot, after a bisect, enabling PECI. This commit in Libreboot adds a patch, reverting coreboot's PECI patch. |
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| .. | ||
| 0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch | ||
| 0002-add-c3-and-clockgen-to-apple-macbook21.patch | ||
| 0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch | ||
| 0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch | ||
| 0005-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch | ||
| 0006-lenovo-x200-set-VRAM-to-352MiB-by-default.patch | ||
| 0007-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch | ||
| 0008-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch | ||
| 0009-Revert-cpu-intel-Configure-IA32_FEATURE_CONTROL-for-.patch | ||
| 0010-Fix-missing-include.patch | ||
| 0011-lenovo-t400-Enable-all-SATA-ports.patch | ||
| 0012-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch | ||