115 lines
3.2 KiB
C
115 lines
3.2 KiB
C
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#include <stdint.h>
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#include <device/pci_ops.h>
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#define IO_MEM_PORT_DECODE_ENABLE_5 0x48
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#define IO_MEM_PORT_DECODE_ENABLE_6 0x4a
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#define SPI_BASE_ADDRESS 0xa0
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#define SPI_CONTROL_1 0xc
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#define TEMPORARY_SPI_BASE_ADDRESS 0xfec10000
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/*
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* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
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*
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* Hardware should enable LPC ROM by pin straps. This function does not
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* handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
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*
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* The SB700 power-on default is to map 512K ROM space.
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*
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* Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00,
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* PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page 14.
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*/
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static void sb700_enable_rom(void)
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{
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u8 reg8;
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u32 dword;
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pci_devfn_t dev;
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dev = PCI_DEV(0, 0x14, 3);
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reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
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if (CONFIG(SPI_FLASH))
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/* Disable decode of variable LPC ROM address ranges 1 and 2. */
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reg8 &= ~((1 << 3) | (1 << 4));
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else
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/* Decode variable LPC ROM address ranges 1 and 2. */
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reg8 |= (1 << 3) | (1 << 4);
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pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
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/* LPC ROM address range 1: */
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/* Enable LPC ROM range mirroring start at 0x000e(0000). */
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pci_io_write_config16(dev, 0x68, 0x000e);
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/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
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pci_io_write_config16(dev, 0x6a, 0x000f);
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/* LPC ROM address range 2: */
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/*
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* Enable LPC ROM range start at:
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* 0xfff8(0000): 512KB
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* 0xfff0(0000): 1MB
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* 0xffe0(0000): 2MB
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* 0xffc0(0000): 4MB
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* 0xff80(0000): 8MB
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*/
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pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
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/* Enable LPC ROM range end at 0xffff(ffff). */
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pci_io_write_config16(dev, 0x6e, 0xffff);
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/* SB700 LPC Bridge 0x48.
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* Turn on all LPC IO Port decode enables
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*/
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pci_io_write_config32(dev, 0x44, 0xffffffff);
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/* SB700 LPC Bridge 0x48.
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* BIT0: Port Enable for SuperIO 0x2E-0x2F
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* BIT1: Port Enable for SuperIO 0x4E-0x4F
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* BIT6: Port Enable for RTC IO 0x70-0x73
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*/
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reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
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reg8 |= (1 << 0) | (1 << 1) | (1 << 6);
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pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
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/* SB700 LPC Bridge 0x4a.
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* BIT5: Port Enable for Port 0x80
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*/
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reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6);
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reg8 |= (1 << 5);
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pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
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}
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static void sb700_configure_rom(void)
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{
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pci_devfn_t dev;
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uint32_t dword;
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dev = PCI_DEV(0, 0x14, 3);
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if (CONFIG(SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) {
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uint32_t prev_spi_cfg;
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volatile uint32_t *spi_mmio;
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/* Temporarily set up SPI access to change SPI speed */
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prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS);
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dword &= ~(0x7ffffff << 5); /* SPI_BaseAddr */
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dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5);
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dword |= (0x1 << 1); /* SpiRomEnable = 1 */
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pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword);
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spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1);
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dword = *spi_mmio;
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dword &= ~(0x3 << 12); /* NormSpeed = 0x1 */
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dword |= (0x1 << 12);
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*spi_mmio = dword;
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/* Restore previous SPI access */
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pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg);
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}
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}
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static void bootblock_southbridge_init(void)
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{
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sb700_enable_rom();
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sb700_configure_rom();
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}
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