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Adrien Bourmault 2024-08-25 11:54:54 +02:00
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58
bibliographie.bib
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@ -1156,3 +1156,61 @@ note = "[Online; accessed 17-August-2024]"
pages={210-225}, pages={210-225},
year={2019} year={2019}
} }
@misc{burnett_ddr3,
author = {Jon Burnett},
title = {DDR3 Design Considerations for PCB Applications (AN111)},
year = {2009},
month = {July},
howpublished = {Presentation at Freescale Technology Forum},
note = {Freescale Semiconductor, Inc.},
}
@inproceedings{kim2010design,
author = {Kim, Dong-Seok and Oh, Dong-Seok and Lee, Seok-Hoon},
title = {Design DDR3 ZQ Calibration having improved impedance matching},
booktitle = {Proceedings of the 2010 Fall Conference on Semiconductor and Display Technology},
year = {2010},
address = {Seoul, South Korea},
pages = {191-192},
publisher = {Hanyang University},
note = {Retrieved from https://koreascience.kr/article/CFKO200835536002505.pdf}
}
@mastersthesis{gopikrishna2021novel,
title = {A Novel Impedance Calibration Method for Low Cost Memory Applications},
author = {Gopikrishna, Siddula},
year = {2021},
school = {International Institute of Information Technology, Hyderabad},
type = {Master of Science Thesis},
address = {Hyderabad, India},
month = {February},
url = {https://cdn.iiit.ac.in/cdn/web2py.iiit.ac.in/research_centres/publications/download/mastersthesis.pdf.a761b452d5c4ae57.476f70696b726973686e615f4d537468657369735f3230303935303034392e706466.pdf},
note = {Accessed: 2024-08-24}
}
@misc{osdev_uefi_memory,
author = "{OSDev Wiki contributors}",
title = "{UEFI - OSDev Wiki}",
year = "2024",
url = "https://wiki.osdev.org/UEFI#Memory",
note = "[Online; accessed 25-August-2024]"
}
@manual{intel_acpi_introduction_2023,
title = {Introduction to ACPI},
author = {Intel Corporation},
year = {2023},
month = {April},
note = {Accessed: 2024-08-24},
url = {https://cdrdv2.intel.com/v1/dl/getContent/772721}
}
@manual{intel_acpi_programming_2023,
title = {ACPI Programming Reference},
author = {Intel Corporation},
year = {2023},
month = {April},
note = {Accessed: 2024-08-24},
url = {https://cdrdv2.intel.com/v1/dl/getContent/772726}
}

206
hardware_init_review.bbl
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@ -139,7 +139,6 @@
\field{number}{AN-520-1.0} \field{number}{AN-520-1.0}
\field{title}{DDR3 SDRAM Memory Interface Termination and Layout Guidelines} \field{title}{DDR3 SDRAM Memory Interface Termination and Layout Guidelines}
\field{year}{2008} \field{year}{2008}
\true{nocite}
\endentry \endentry
\entry{amd_ddr3_guide}{manual}{} \entry{amd_ddr3_guide}{manual}{}
\name{author}{1}{}{% \name{author}{1}{}{%
@ -531,6 +530,30 @@
\field{pages}{45\bibrangedash 56} \field{pages}{45\bibrangedash 56}
\range{pages}{12} \range{pages}{12}
\endentry \endentry
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{{hash=70ed1943e8d3a50c06615ef57a082097}{%
family={Burnett},
familyi={B\bibinitperiod},
given={Jon},
giveni={J\bibinitperiod}}}%
}
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\field{note}{Freescale Semiconductor, Inc.}
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\field{year}{2009}
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{{hash=701500fa4f83c75c8ce39152916ce4e4}{% {{hash=701500fa4f83c75c8ce39152916ce4e4}{%
@ -691,6 +714,37 @@
\verb https://doc.coreboot.org/memory-map.html \verb https://doc.coreboot.org/memory-map.html
\endverb \endverb
\endentry \endentry
\entry{intel_acpi_programming_2023}{manual}{}
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{{hash=42af28f239d9ce2a4d0f9a032741150e}{%
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\field{note}{Accessed: 2024-08-24}
\field{title}{ACPI Programming Reference}
\field{year}{2023}
\true{nocite}
\verb{urlraw}
\verb https://cdrdv2.intel.com/v1/dl/getContent/772726
\endverb
\verb{url}
\verb https://cdrdv2.intel.com/v1/dl/getContent/772726
\endverb
\endentry
\entry{intel_acpi_spec}{book}{} \entry{intel_acpi_spec}{book}{}
\name{author}{1}{}{% \name{author}{1}{}{%
{{hash=42af28f239d9ce2a4d0f9a032741150e}{% {{hash=42af28f239d9ce2a4d0f9a032741150e}{%
@ -708,7 +762,7 @@
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@ -736,7 +790,7 @@
\strng{authorbibnamehash}{42af28f239d9ce2a4d0f9a032741150e} \strng{authorbibnamehash}{42af28f239d9ce2a4d0f9a032741150e}
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@ -751,6 +805,37 @@
\verb https://software.intel.com/content/dam/www/public/us/en/security-advisory/documents/intel-csme-security-white-paper.pdf \verb https://software.intel.com/content/dam/www/public/us/en/security-advisory/documents/intel-csme-security-white-paper.pdf
\endverb \endverb
\endentry \endentry
\entry{intel_acpi_introduction_2023}{manual}{}
\name{author}{1}{}{%
{{hash=42af28f239d9ce2a4d0f9a032741150e}{%
family={Corporation},
familyi={C\bibinitperiod},
given={Intel},
giveni={I\bibinitperiod}}}%
}
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\field{labelnamesource}{author}
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\field{month}{4}
\field{note}{Accessed: 2024-08-24}
\field{title}{Introduction to ACPI}
\field{year}{2023}
\true{nocite}
\verb{urlraw}
\verb https://cdrdv2.intel.com/v1/dl/getContent/772721
\endverb
\verb{url}
\verb https://cdrdv2.intel.com/v1/dl/getContent/772721
\endverb
\endentry
\entry{intel_smm}{report}{} \entry{intel_smm}{report}{}
\name{author}{1}{}{% \name{author}{1}{}{%
{{hash=42af28f239d9ce2a4d0f9a032741150e}{% {{hash=42af28f239d9ce2a4d0f9a032741150e}{%
@ -765,7 +850,7 @@
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@ -795,7 +880,7 @@
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@ -818,7 +903,7 @@
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@ -1166,6 +1251,42 @@
\field{title}{Fire in the Valley: The Birth and Death of the Personal Computer} \field{title}{Fire in the Valley: The Birth and Death of the Personal Computer}
\field{year}{2000} \field{year}{2000}
\endentry \endentry
\entry{gopikrishna2021novel}{thesis}{}
\name{author}{1}{}{%
{{hash=9867142dbcfb52fac76189436d952c3c}{%
family={Gopikrishna},
familyi={G\bibinitperiod},
given={Siddula},
giveni={S\bibinitperiod}}}%
}
\list{institution}{1}{%
{International Institute of Information Technology, Hyderabad}%
}
\list{location}{1}{%
{Hyderabad, India}%
}
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\field{note}{Accessed: 2024-08-24}
\field{title}{A Novel Impedance Calibration Method for Low Cost Memory Applications}
\field{type}{Master of Science Thesis}
\field{year}{2021}
\verb{urlraw}
\verb https://cdn.iiit.ac.in/cdn/web2py.iiit.ac.in/research_centres/publications/download/mastersthesis.pdf.a761b452d5c4ae57.476f70696b726973686e615f4d537468657369735f3230303935303034392e706466.pdf
\endverb
\verb{url}
\verb https://cdn.iiit.ac.in/cdn/web2py.iiit.ac.in/research_centres/publications/download/mastersthesis.pdf.a761b452d5c4ae57.476f70696b726973686e615f4d537468657369735f3230303935303034392e706466.pdf
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\entry{blackhat_me_hack}{article}{} \entry{blackhat_me_hack}{article}{}
\name{author}{2}{}{% \name{author}{2}{}{%
{{hash=e450be1043f8bd6abbfc1a479f2d7700}{% {{hash=e450be1043f8bd6abbfc1a479f2d7700}{%
@ -1419,7 +1540,6 @@
\field{number}{TN-41-02} \field{number}{TN-41-02}
\field{title}{Technical Note: DDR3 ZQ Calibration} \field{title}{Technical Note: DDR3 ZQ Calibration}
\field{year}{2008} \field{year}{2008}
\true{nocite}
\endentry \endentry
\entry{intel_me}{misc}{} \entry{intel_me}{misc}{}
\name{author}{1}{}{% \name{author}{1}{}{%
@ -1566,6 +1686,47 @@
\verb 10.1145/2851141.2851148 \verb 10.1145/2851141.2851148
\endverb \endverb
\endentry \endentry
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\name{author}{3}{}{%
{{hash=8220787d0eaa6f1c680840bf616c1cf4}{%
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{{hash=f73fbd8e5fd85d5a4945843500511870}{%
family={Lee},
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}
\list{location}{1}{%
{Seoul, South Korea}%
}
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{Hanyang University}%
}
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\field{booktitle}{Proceedings of the 2010 Fall Conference on Semiconductor and Display Technology}
\field{note}{Retrieved from https://koreascience.kr/article/CFKO200835536002505.pdf}
\field{title}{Design DDR3 ZQ Calibration having improved impedance matching}
\field{year}{2010}
\field{pages}{191\bibrangedash 192}
\range{pages}{2}
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\name{author}{3}{}{% \name{author}{3}{}{%
{{hash=0f5d712d2df5a2eb138c92b8957c02fe}{% {{hash=0f5d712d2df5a2eb138c92b8957c02fe}{%
@ -1838,7 +1999,6 @@
\field{number}{TN-41-02} \field{number}{TN-41-02}
\field{title}{DDR3 SDRAM Specification Rev 1.4} \field{title}{DDR3 SDRAM Specification Rev 1.4}
\field{year}{2011} \field{year}{2011}
\true{nocite}
\endentry \endentry
\entry{blobs}{misc}{} \entry{blobs}{misc}{}
\name{author}{1}{}{% \name{author}{1}{}{%
@ -2347,6 +2507,33 @@
\verb https://wiki.osdev.org/GOP \verb https://wiki.osdev.org/GOP
\endverb \endverb
\endentry \endentry
\entry{osdev_uefi_memory}{misc}{}
\name{author}{1}{}{%
{{hash=981adb9ea98beb2d8a06e293991365f1}{%
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\field{note}{[Online; accessed 25-August-2024]}
\field{title}{{UEFI - OSDev Wiki}}
\field{year}{2024}
\true{nocite}
\verb{urlraw}
\verb https://wiki.osdev.org/UEFI#Memory
\endverb
\verb{url}
\verb https://wiki.osdev.org/UEFI#Memory
\endverb
\endentry
\entry{pearson2014}{inproceedings}{} \entry{pearson2014}{inproceedings}{}
\name{author}{1}{}{% \name{author}{1}{}{%
{{hash=0cb7f02abd4eddb75a923fdbd4722b97}{% {{hash=0cb7f02abd4eddb75a923fdbd4722b97}{%
@ -2858,7 +3045,6 @@
\field{title}{Memory Errors in Modern Systems: The Good, The Bad, and The Ugly} \field{title}{Memory Errors in Modern Systems: The Good, The Bad, and The Ugly}
\field{volume}{43} \field{volume}{43}
\field{year}{2015} \field{year}{2015}
\true{nocite}
\field{pages}{297\bibrangedash 310} \field{pages}{297\bibrangedash 310}
\range{pages}{14} \range{pages}{14}
\endentry \endentry
@ -3339,7 +3525,6 @@
\field{note}{[Online; accessed 8-May-2024]} \field{note}{[Online; accessed 8-May-2024]}
\field{title}{DDR3 SDRAM --- {Wikipedia}{,} The Free Encyclopedia} \field{title}{DDR3 SDRAM --- {Wikipedia}{,} The Free Encyclopedia}
\field{year}{2024} \field{year}{2024}
\true{nocite}
\verb{urlraw} \verb{urlraw}
\verb https://en.wikipedia.org/w/index.php?title=DDR3_SDRAM&oldid=1207641521 \verb https://en.wikipedia.org/w/index.php?title=DDR3_SDRAM&oldid=1207641521
\endverb \endverb
@ -3858,6 +4043,7 @@
\field{title}{Modern Boot Firmware: Moving from BIOS to UEFI} \field{title}{Modern Boot Firmware: Moving from BIOS to UEFI}
\field{volume}{39} \field{volume}{39}
\field{year}{2006} \field{year}{2006}
\true{nocite}
\field{pages}{42\bibrangedash 47} \field{pages}{42\bibrangedash 47}
\range{pages}{6} \range{pages}{6}
\verb{doi} \verb{doi}

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hardware_init_review.tex
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93
hardware_init_review.toc
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@ -1,43 +1,52 @@
\babel@toc {english}{}\relax \babel@toc {english}{}\relax
\contentsline {chapter}{Abstract}{5}{chapter*.1}% \contentsline {chapter}{Acknowledgments}{3}{chapter*.1}%
\contentsline {chapter}{\numberline {1}Introduction to firmware and BIOS evolution}{6}{chapter.1}% \contentsline {chapter}{Abstract}{4}{chapter*.2}%
\contentsline {section}{\numberline {1.1}Historical context of BIOS}{6}{section.1.1}% \contentsline {chapter}{List of Figures}{7}{chapter*.2}%
\contentsline {subsection}{\numberline {1.1.1}Definition and origin}{6}{subsection.1.1.1}% \contentsline {chapter}{List of Listings}{8}{chapter*.2}%
\contentsline {subsection}{\numberline {1.1.2}Functionalities and limitations}{7}{subsection.1.1.2}% \contentsline {chapter}{\numberline {1}Introduction to firmware and BIOS evolution}{9}{chapter.1}%
\contentsline {section}{\numberline {1.2}Modern BIOS and UEFI}{8}{section.1.2}% \contentsline {section}{\numberline {1.1}Historical context of BIOS}{9}{section.1.1}%
\contentsline {subsection}{\numberline {1.2.1}Transition from traditional BIOS to UEFI (Unified Extensible Firmware Interface)}{8}{subsection.1.2.1}% \contentsline {subsection}{\numberline {1.1.1}Definition and origin}{9}{subsection.1.1.1}%
\contentsline {subsection}{\numberline {1.2.2}An other way with \textit {coreboot}}{8}{subsection.1.2.2}% \contentsline {subsection}{\numberline {1.1.2}Functionalities and limitations}{10}{subsection.1.1.2}%
\contentsline {section}{\numberline {1.3}Shift in firmware responsibilities}{10}{section.1.3}% \contentsline {section}{\numberline {1.2}Modern BIOS and UEFI}{11}{section.1.2}%
\contentsline {chapter}{\numberline {2}Characteristics of ASUS KGPE-D16 mainboard}{11}{chapter.2}% \contentsline {subsection}{\numberline {1.2.1}Transition from traditional BIOS to UEFI (Unified Extensible Firmware Interface)}{11}{subsection.1.2.1}%
\contentsline {section}{\numberline {2.1}Overview of ASUS KGPE-D16 hardware}{12}{section.2.1}% \contentsline {subsection}{\numberline {1.2.2}An other way with \textit {coreboot}}{11}{subsection.1.2.2}%
\contentsline {section}{\numberline {2.2}Chipset}{13}{section.2.2}% \contentsline {section}{\numberline {1.3}Shift in firmware responsibilities}{13}{section.1.3}%
\contentsline {section}{\numberline {2.3}Processors}{15}{section.2.3}% \contentsline {chapter}{\numberline {2}Characteristics of ASUS KGPE-D16 mainboard}{14}{chapter.2}%
\contentsline {section}{\numberline {2.4}Baseboard Management Controller}{16}{section.2.4}% \contentsline {section}{\numberline {2.1}Overview of ASUS KGPE-D16 hardware}{15}{section.2.1}%
\contentsline {chapter}{\numberline {3}Key components in modern firmware}{18}{chapter.3}% \contentsline {section}{\numberline {2.2}Chipset}{16}{section.2.2}%
\contentsline {section}{\numberline {3.1}General structure of coreboot}{18}{section.3.1}% \contentsline {section}{\numberline {2.3}Processors}{18}{section.2.3}%
\contentsline {subsection}{\numberline {3.1.1}Bootblock stage}{19}{subsection.3.1.1}% \contentsline {section}{\numberline {2.4}Baseboard Management Controller}{19}{section.2.4}%
\contentsline {subsection}{\numberline {3.1.2}Romstage}{21}{subsection.3.1.2}% \contentsline {chapter}{\numberline {3}Key components in modern firmware}{21}{chapter.3}%
\contentsline {subsection}{\numberline {3.1.3}Ramstage}{22}{subsection.3.1.3}% \contentsline {section}{\numberline {3.1}General structure of coreboot}{21}{section.3.1}%
\contentsline {subsubsection}{\numberline {3.1.3.1}Advanced Configuration and Power Interface}{22}{subsubsection.3.1.3.1}% \contentsline {subsection}{\numberline {3.1.1}Bootblock stage}{22}{subsection.3.1.1}%
\contentsline {subsubsection}{\numberline {3.1.3.2}System Management Mode}{23}{subsubsection.3.1.3.2}% \contentsline {subsection}{\numberline {3.1.2}Romstage}{24}{subsection.3.1.2}%
\contentsline {subsection}{\numberline {3.1.4}Payload}{23}{subsection.3.1.4}% \contentsline {subsection}{\numberline {3.1.3}Ramstage}{25}{subsection.3.1.3}%
\contentsline {section}{\numberline {3.2}AMD Platform Security Processor and Intel Management Engine}{24}{section.3.2}% \contentsline {subsubsection}{\numberline {3.1.3.1}Advanced Configuration and Power Interface}{25}{subsubsection.3.1.3.1}%
\contentsline {chapter}{\numberline {4}Memory initialization and training algorithms [WIP]}{26}{chapter.4}% \contentsline {subsubsection}{\numberline {3.1.3.2}System Management Mode}{26}{subsubsection.3.1.3.2}%
\contentsline {section}{\numberline {4.1}Importance of memory initialization}{26}{section.4.1}% \contentsline {subsection}{\numberline {3.1.4}Payload}{26}{subsection.3.1.4}%
\contentsline {section}{\numberline {4.2}Memory training algorithms}{26}{section.4.2}% \contentsline {section}{\numberline {3.2}AMD Platform Security Processor and Intel Management Engine}{27}{section.3.2}%
\contentsline {section}{\numberline {4.3}Practical examples}{27}{section.4.3}% \contentsline {chapter}{\numberline {4}Memory initialization and training}{29}{chapter.4}%
\contentsline {subsection}{\numberline {4.3.1}RAM Initialization Preparation}{27}{subsection.4.3.1}% \contentsline {section}{\numberline {4.1}Importance of DDR3 Memory Initialization}{29}{section.4.1}%
\contentsline {subsection}{\numberline {4.3.2}RAM Initialization}{27}{subsection.4.3.2}% \contentsline {subsection}{\numberline {4.1.1}General steps for DDR3 configuration}{30}{subsection.4.1.1}%
\contentsline {subsubsection}{\numberline {4.3.2.1}Memory Controller Initialization}{27}{subsubsection.4.3.2.1}% \contentsline {section}{\numberline {4.2}Memory initialization techniques}{32}{section.4.2}%
\contentsline {subsubsection}{\numberline {4.3.2.2}Memory Module Training}{28}{subsubsection.4.3.2.2}% \contentsline {subsection}{\numberline {4.2.1}Memory training algorithms}{32}{subsection.4.2.1}%
\contentsline {chapter}{\numberline {5}Virtualization of the operating system through firmware abstraction}{29}{chapter.5}% \contentsline {subsection}{\numberline {4.2.2}BIOS and Kernel Developer Guide (BKDG) recommendations}{33}{subsection.4.2.2}%
\contentsline {section}{\numberline {5.1}ACPI and abstraction of hardware control}{29}{section.5.1}% \contentsline {subsubsection}{\numberline {4.2.2.1}DDR3 initialization procedure}{34}{subsubsection.4.2.2.1}%
\contentsline {section}{\numberline {5.2}SMM as a hidden execution layer}{29}{section.5.2}% \contentsline {subsubsection}{\numberline {4.2.2.2}ZQ calibration process}{34}{subsubsection.4.2.2.2}%
\contentsline {section}{\numberline {5.3}UEFI and persistence}{29}{section.5.3}% \contentsline {subsubsection}{\numberline {4.2.2.3}Write leveling process}{35}{subsubsection.4.2.2.3}%
\contentsline {section}{\numberline {5.4}Intel and AMD: control beyond the OS}{30}{section.5.4}% \contentsline {section}{\numberline {4.3}Current implementation and potential improvements [WIP]}{36}{section.4.3}%
\contentsline {section}{\numberline {5.5}The OS as a virtualized environment}{30}{section.5.5}% \contentsline {subsection}{\numberline {4.3.1}Current implementation in coreboot on the KGPE-D16 [WIP]}{36}{subsection.4.3.1}%
\contentsline {chapter}{Conclusion}{31}{chapter*.2}% \contentsline {subsection}{\numberline {4.3.2}Potential enhancements [WIP]}{37}{subsection.4.3.2}%
\contentsline {chapter}{Bibliography}{32}{chapter*.2}% \contentsline {chapter}{\numberline {5}Virtualization of the operating system through firmware abstraction}{38}{chapter.5}%
\contentsline {chapter}{List of Figures}{38}{chapter*.3}% \contentsline {section}{\numberline {5.1}ACPI and abstraction of hardware control}{38}{section.5.1}%
\contentsline {chapter}{List of Listings}{39}{chapter*.3}% \contentsline {section}{\numberline {5.2}SMM as a hidden execution layer}{39}{section.5.2}%
\contentsline {chapter}{GNU Free Documentation License}{40}{chapter*.5}% \contentsline {section}{\numberline {5.3}UEFI and persistence}{39}{section.5.3}%
\contentsline {subsection}{\numberline {5.3.1}Memory Management}{40}{subsection.5.3.1}%
\contentsline {subsection}{\numberline {5.3.2}File System Management}{40}{subsection.5.3.2}%
\contentsline {subsection}{\numberline {5.3.3}Device Drivers}{40}{subsection.5.3.3}%
\contentsline {subsection}{\numberline {5.3.4}Power Management}{40}{subsection.5.3.4}%
\contentsline {section}{\numberline {5.4}Intel and AMD: control beyond the OS}{40}{section.5.4}%
\contentsline {section}{\numberline {5.5}The OS as a virtualized environment}{41}{section.5.5}%
\contentsline {chapter}{Conclusion}{42}{chapter*.4}%
\contentsline {chapter}{Bibliography}{43}{chapter*.4}%
\contentsline {chapter}{GNU Free Documentation License}{50}{chapter*.6}%

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$ git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
$ cd linux/drivers/acpi
$ find . -name "*.c" -o -name "*.h" | xargs wc -l
[...]
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\usepackage{chngcntr} \usepackage{chngcntr}
\usepackage{changepage} \usepackage{changepage}
\usepackage{array} \usepackage{array}
\usepackage{tikz}
\usetikzlibrary{automata, positioning}
\usepackage[a4paper, portrait, margin=1.45cm]{geometry} \usepackage[a4paper, portrait, margin=1.45cm]{geometry}
\title{Titre du mémoire}
\author{Nom et prénom de l'auteur}
\date{\today}
% Set parameters % Set parameters
\setcounter{page}{0} \setcounter{page}{0}