Misc enhancements

hardware_init_review.tex

@@ -1542,7 +1542,7 @@
             is essential for achieving the desired balance of performance,
             reliability, and stability in demanding server environments.
 
-        \subsection{General steps for DDR3 configuration}
+    \section{General steps for DDR3 configuration}
 
         DDR3 memory initialization is a detailed and essential
         process that ensures both the stability and performance of the
@@ -3468,7 +3468,7 @@ uint8_t AddrCmdPrelaunch = 0;   /* TODO: Fetch the correct value from RC2[0] */
  * 0x41 and 0x0 are the "stock" values */
                         \end{minted}
                     \end{adjustwidth}
-                \caption{\texttt{FIXME} indicating the need for
+                \caption{Lack of
                     mainboard-specific seed overrides,
                     extract from
                     \protect\path{procConfig} function in
@@ -3562,7 +3562,7 @@ if (faulty_value_detected) {
                 code. The overcomplicated logic can also make the code more
                 difficult to maintain and extend. \\
 
-            \subsection{DQS position training}
+            \subsubsection{DQS position training}
 
                 While the DQS position training algorithm implemented in the
                 \path{TrainDQSRdWrPos_D_Fam15} function may work in some
@@ -3714,9 +3714,7 @@ if (best_count > 2) {
                 the time required for DQS position training without compromising
                 accuracy. \\
 
-            \subsection{On a wider scale...}
+            \subsubsection{On saving training values in NVRAM}
-
-                \subsubsection{Saving training values in NVRAM}
 
                 The function \path{mctAutoInitMCT_D} is responsible for
                 automatically initializing the memory controller training (MCT)
@@ -4219,7 +4217,8 @@ if (best_count > 2) {
 
 \chapter*{Appendix: Long code listings}
 \addcontentsline{toc}{chapter}{Appendix: Long code listings}
-\renewcommand{\thelisting}{\arabic{listing}}
+\renewcommand{\thelisting}{L.\arabic{listing}}
+\setcounter{listing}{0}
 
     \begin{listing}
     \begin{adjustwidth}{0.5cm}{0.5cm}

hardware_init_review.toc

@@ -28,28 +28,25 @@
 \contentsline {section}{\numberline {3.2}AMD Platform Security Processor and Intel Management Engine}{28}{section.3.2}%
 \contentsline {chapter}{\numberline {4}Memory initialization and training}{30}{chapter.4}%
 \contentsline {section}{\numberline {4.1}Importance of DDR3 memory initialization}{30}{section.4.1}%
-\contentsline {subsection}{\numberline {4.1.1}General steps for DDR3 configuration}{31}{subsection.4.1.1}%
+\contentsline {section}{\numberline {4.2}General steps for DDR3 configuration}{31}{section.4.2}%
-\contentsline {section}{\numberline {4.2}Memory initialization techniques}{34}{section.4.2}%
+\contentsline {section}{\numberline {4.3}Memory initialization techniques}{34}{section.4.3}%
-\contentsline {subsection}{\numberline {4.2.1}Memory training algorithms}{34}{subsection.4.2.1}%
+\contentsline {subsection}{\numberline {4.3.1}Memory training algorithms}{34}{subsection.4.3.1}%
-\contentsline {subsection}{\numberline {4.2.2}BIOS and Kernel Developer Guide (BKDG) recommendations}{35}{subsection.4.2.2}%
+\contentsline {subsection}{\numberline {4.3.2}BIOS and Kernel Developer Guide (BKDG) recommendations}{35}{subsection.4.3.2}%
-\contentsline {subsubsection}{\numberline {4.2.2.1}DDR3 initialization procedure}{36}{subsubsection.4.2.2.1}%
+\contentsline {subsubsection}{\numberline {4.3.2.1}DDR3 initialization procedure}{36}{subsubsection.4.3.2.1}%
-\contentsline {subsubsection}{\numberline {4.2.2.2}ZQ calibration process}{36}{subsubsection.4.2.2.2}%
+\contentsline {subsubsection}{\numberline {4.3.2.2}ZQ calibration process}{36}{subsubsection.4.3.2.2}%
-\contentsline {subsubsection}{\numberline {4.2.2.3}Write leveling process}{37}{subsubsection.4.2.2.3}%
+\contentsline {subsubsection}{\numberline {4.3.2.3}Write leveling process}{37}{subsubsection.4.3.2.3}%
-\contentsline {section}{\numberline {4.3}Current implementation and potential improvements}{39}{section.4.3}%
+\contentsline {section}{\numberline {4.4}Current implementation and potential improvements}{39}{section.4.4}%
-\contentsline {subsection}{\numberline {4.3.1}Current implementation in coreboot on the KGPE-D16}{39}{subsection.4.3.1}%
+\contentsline {subsection}{\numberline {4.4.1}Current implementation in coreboot on the KGPE-D16}{39}{subsection.4.4.1}%
-\contentsline {subsubsection}{\numberline {4.3.1.1}Details on the DQS training function}{41}{subsubsection.4.3.1.1}%
+\contentsline {subsubsection}{\numberline {4.4.1.1}Details on the DQS training function}{41}{subsubsection.4.4.1.1}%
-\contentsline {subsubsection}{\numberline {4.3.1.2}Details on the write leveling implementation}{43}{subsubsection.4.3.1.2}%
+\contentsline {subsubsection}{\numberline {4.4.1.2}Details on the write leveling implementation}{43}{subsubsection.4.4.1.2}%
-\contentsline {subsubsection}{\numberline {4.3.1.3}Details on the write leveling implementation}{44}{subsubsection.4.3.1.3}%
+\contentsline {subsubsection}{\numberline {4.4.1.3}Details on the DQS position training function}{45}{subsubsection.4.4.1.3}%
-\contentsline {subsection}{\numberline {4.3.2}Write Leveling on AMD Fam15h G34 Processors with RDIMMs}{44}{subsection.4.3.2}%
+\contentsline {subsubsection}{\numberline {4.4.1.4}Details on the DQS receiver training function}{47}{subsubsection.4.4.1.4}%
-\contentsline {subsubsection}{\numberline {4.3.2.1}Details on the DQS position training function}{45}{subsubsection.4.3.2.1}%
+\contentsline {subsection}{\numberline {4.4.2}Potential enhancements}{50}{subsection.4.4.2}%
-\contentsline {subsubsection}{\numberline {4.3.2.2}Details on the DQS receiver training function}{48}{subsubsection.4.3.2.2}%
+\contentsline {subsubsection}{\numberline {4.4.2.1}DQS receiver training}{50}{subsubsection.4.4.2.1}%
-\contentsline {subsection}{\numberline {4.3.3}Potential enhancements}{50}{subsection.4.3.3}%
+\contentsline {subsubsection}{\numberline {4.4.2.2}Write leveling}{52}{subsubsection.4.4.2.2}%
-\contentsline {subsubsection}{\numberline {4.3.3.1}DQS receiver training}{50}{subsubsection.4.3.3.1}%
+\contentsline {subsubsection}{\numberline {4.4.2.3}DQS position training}{54}{subsubsection.4.4.2.3}%
-\contentsline {subsubsection}{\numberline {4.3.3.2}Write leveling}{52}{subsubsection.4.3.3.2}%
+\contentsline {subsubsection}{\numberline {4.4.2.4}On saving training values in NVRAM}{56}{subsubsection.4.4.2.4}%
-\contentsline {subsection}{\numberline {4.3.4}DQS position training}{54}{subsection.4.3.4}%
+\contentsline {subsubsection}{\numberline {4.4.2.5}A seedless DQS position training algorithm}{57}{subsubsection.4.4.2.5}%
-\contentsline {subsection}{\numberline {4.3.5}On a wider scale...}{56}{subsection.4.3.5}%
-\contentsline {subsubsection}{\numberline {4.3.5.1}Saving training values in NVRAM}{56}{subsubsection.4.3.5.1}%
-\contentsline {subsubsection}{\numberline {4.3.5.2}A seedless DQS position training algorithm}{57}{subsubsection.4.3.5.2}%
 \contentsline {chapter}{\numberline {5}Virtualization of the operating system through firmware abstraction}{59}{chapter.5}%
 \contentsline {section}{\numberline {5.1}ACPI and abstraction of hardware control}{59}{section.5.1}%
 \contentsline {section}{\numberline {5.2}SMM as a hidden execution layer}{60}{section.5.2}%

packages.tex

@@ -33,18 +33,29 @@
     \usepackage[a4paper, portrait, margin=1.45cm]{geometry}
 
 % Set parameters
+
+% No warnings
 \WarningsOff
 
+% No message for text justification
+\hbadness=10000
+
+% Start at page 0
 \setcounter{page}{0}
+
+% Link every toc element
 \hypersetup{linktoc=all}
 
+% Enhance footnotes
 \addtolength{\skip\footins}{0.6pc}
 \renewcommand*\footnoterule{} %Footnode separator line
 
 %\def\siecle#1{\textsc{\romannumeral #1}\textsuperscript{e}~siècle}
 
+% Place dots on sections in toc
 \renewcommand{\cftsecleader}{\cftdotfill{\cftdotsep}} %places dots on sections lines as well
 
+% Tweak auto-tabulations
 \cftsetindents{section}{0pt}{4em}
 \cftsetindents{subsection}{10pt}{4em}
 \cftsetindents{subsubsection}{20pt}{4em}
@@ -52,12 +63,15 @@
 \cftsetindents{subparagraph}{40pt}{4em}
 \def\cftdotsep{1}
 \cftsetpnumwidth{1em}
-
-\renewcommand{\cftchapafterpnum}{\vspace{\cftbeforechapskip}}
-\renewcommand{\familydefault}{\sfdefault}
-
 \setlength\parindent{0pt}
 
+% Defaults space before chapters
+\renewcommand{\cftchapafterpnum}{\vspace{\cftbeforechapskip}}
+
+% Sans-serif, of course
+\renewcommand{\familydefault}{\sfdefault}
+
+% Configure listings
 \usemintedstyle{solarized-light}
 \definecolor{bg}{HTML}{FAF9F6}
 \definecolor{linenumcolor}{rgb}{0.6, 0.6, 0.6}  % Light gray color