diff --git a/hardware_init_review.pdf b/hardware_init_review.pdf
index 9199a78..0f64c35 100644
Binary files a/hardware_init_review.pdf and b/hardware_init_review.pdf differ
diff --git a/hardware_init_review.tex b/hardware_init_review.tex
index 10092a7..0f7e535 100644
--- a/hardware_init_review.tex
+++ b/hardware_init_review.tex
@@ -895,7 +895,7 @@
             specific to AMD processors. It is the first C routine executed, and
             its role is to verify that the current processor is indeed the BSC,
             allowing the function \path{bootblock_main_with_basetime}
-            to be called exclusively by the BSC.
+            to be called exclusively by the BSC. \\
 
             We are now in the file \path{src/lib/bootblock.c}, written by
             Google's team, and entering the
@@ -929,7 +929,7 @@
             then checked (this jumper is intended to reset the CMOS content,
             although it is not fully functional at the moment, as indicated by
             the \texttt{FIXME} comment in the code). Control then returns to
-            \texttt{bootblock\_main} in \path{src/lib/bootblock.c}.
+            \texttt{bootblock\_main} in \path{src/lib/bootblock.c}. \\
 
             At this point, everything is ready to enter the romstage.
             \textit{coreboot} has successfully started and can now continue its
@@ -985,7 +985,8 @@
             SuperIO is then initialized to activate the serial port, allowing
             the serial console to follow \textit{coreboot}’s progress in
             real-time. If everything proceeds as expected, the code 0x30 is
-            sent, and the boot process continues.
+            sent, and the boot process continues. \\
+
             If the result of the Built-in Self-Test (BIST), saved during the
             \textit{bootblock}, shows no anomalies, all cores of all nodes are
             configured, and they are placed back into sleep mode (except for the