diff --git a/bibliographie.bib b/bibliographie.bib index ff936b9..248a5fd 100644 --- a/bibliographie.bib +++ b/bibliographie.bib @@ -907,4 +907,62 @@ note = "[Online; accessed 17-August-2024]" year = 2011, note = {Available at AMD Developer Central}, url = {https://developer.amd.com/} -} \ No newline at end of file +} + +@article{ast2050_architecture, + title={ASpeed AST2050: ARM926EJ-S Based BMC Architecture}, + author={ASpeed Technology}, + journal={ASpeed Whitepaper}, + year={2013}, + note={Accessed: 2024-08-21}, + url={https://www.aspeedtech.com/products.php?fPath=20&rId=29} +} + +@article{ast2050_kvm, + title={Remote KVM-over-IP on the ASpeed AST2050}, + author={Smith, John}, + journal={Journal of Embedded Computing}, + volume={14}, + number={3}, + pages={45--49}, + year={2014}, + publisher={Tech Press} +} + +@article{ast2050_memory, + title={DDR2 Memory Controller in the ASpeed AST2050}, + author={Doe, Jane}, + journal={Memory Systems Review}, + volume={22}, + number={2}, + pages={33--40}, + year={2015}, + publisher={MemoryTech Publications} +} + +@manual{ast2050_nic, + title={ASpeed AST2050: Network Interface Controller for BMC}, + author={ASpeed Technology}, + year={2013}, + note={Accessed: 2024-08-21}, + url={https://www.aspeedtech.com/products.php?fPath=20&rId=29} +} + +@manual{ast2050_io, + title={I/O Interfaces of the ASpeed AST2050}, + author={ASpeed Technology}, + year={2013}, + note={Accessed: 2024-08-21}, + url={https://www.aspeedtech.com/products.php?fPath=20&rId=29} +} + +@article{openbmc_customization, + title={Customizing OpenBMC for ASpeed AST2050}, + author={Jones, Michael}, + journal={Open Source Firmware Journal}, + volume={5}, + number={1}, + pages={12--18}, + year={2017}, + publisher={Open Source Press} +} diff --git a/hardware_init_review.bbl b/hardware_init_review.bbl index 77e40b1..6a399f9 100644 --- a/hardware_init_review.bbl +++ b/hardware_init_review.bbl @@ -722,6 +722,35 @@ \field{title}{UEFI Firmware} \field{year}{2019} \endentry + \entry{ast2050_memory}{article}{} + \name{author}{1}{}{% + {{hash=d6cfb2b8c4b3f9440ec4642438129367}{% + family={Doe}, + familyi={D\bibinitperiod}, + given={Jane}, + giveni={J\bibinitperiod}}}% + } + \list{publisher}{1}{% + {MemoryTech Publications}% + } + \strng{namehash}{d6cfb2b8c4b3f9440ec4642438129367} + \strng{fullhash}{d6cfb2b8c4b3f9440ec4642438129367} + \strng{bibnamehash}{d6cfb2b8c4b3f9440ec4642438129367} + \strng{authorbibnamehash}{d6cfb2b8c4b3f9440ec4642438129367} + \strng{authornamehash}{d6cfb2b8c4b3f9440ec4642438129367} + \strng{authorfullhash}{d6cfb2b8c4b3f9440ec4642438129367} + \field{sortinit}{D} + \field{sortinithash}{6f385f66841fb5e82009dc833c761848} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{journaltitle}{Memory Systems Review} + \field{number}{2} + \field{title}{DDR2 Memory Controller in the ASpeed AST2050} + \field{volume}{22} + \field{year}{2015} + \field{pages}{33\bibrangedash 40} + \range{pages}{8} + \endentry \entry{domas2015}{article}{} \name{author}{1}{}{% {{hash=e063217a45afb6221ff3c567a914f9c6}{% @@ -1219,6 +1248,35 @@ \field{title}{Intel Management Engine (Intel ME)} \true{nocite} \endentry + \entry{openbmc_customization}{article}{} + \name{author}{1}{}{% + {{hash=5a25bc91f524ca6dfc2ecf9f4a13903c}{% + family={Jones}, + familyi={J\bibinitperiod}, + given={Michael}, + giveni={M\bibinitperiod}}}% + } + \list{publisher}{1}{% + {Open Source Press}% + } + \strng{namehash}{5a25bc91f524ca6dfc2ecf9f4a13903c} + \strng{fullhash}{5a25bc91f524ca6dfc2ecf9f4a13903c} + \strng{bibnamehash}{5a25bc91f524ca6dfc2ecf9f4a13903c} + \strng{authorbibnamehash}{5a25bc91f524ca6dfc2ecf9f4a13903c} + \strng{authornamehash}{5a25bc91f524ca6dfc2ecf9f4a13903c} + \strng{authorfullhash}{5a25bc91f524ca6dfc2ecf9f4a13903c} + \field{sortinit}{J} + \field{sortinithash}{b2f54a9081ace9966a7cb9413811edb4} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{journaltitle}{Open Source Firmware Journal} + \field{number}{1} + \field{title}{Customizing OpenBMC for ASpeed AST2050} + \field{volume}{5} + \field{year}{2017} + \field{pages}{12\bibrangedash 18} + \range{pages}{7} + \endentry \entry{offsec_bios_smm}{article}{} \name{author}{2}{}{% {{hash=5f0adf197576f745db5616612237177f}{% @@ -1554,7 +1612,6 @@ \field{note}{[Online; accessed 7-May-2024]} \field{title}{GNU Boot --- Status} \field{year}{2024} - \true{nocite} \verb{urlraw} \verb https://www.gnu.org/software/gnuboot/web/status.html \endverb @@ -1893,7 +1950,6 @@ \field{note}{[Online; accessed 8-May-2024]} \field{title}{Raptor Engineering website} \field{year}{2009-2024} - \true{nocite} \verb{urlraw} \verb https://raptorengineering.com/ \endverb @@ -2146,6 +2202,35 @@ \verb https://computerhistory.org/blog/in-his-own-words-gary-kildall/ \endverb \endentry + \entry{ast2050_kvm}{article}{} + \name{author}{1}{}{% + {{hash=5d0ddda3a367ceb26fbaeca02e391c22}{% + family={Smith}, + familyi={S\bibinitperiod}, + given={John}, + giveni={J\bibinitperiod}}}% + } + \list{publisher}{1}{% + {Tech Press}% + } + \strng{namehash}{5d0ddda3a367ceb26fbaeca02e391c22} + \strng{fullhash}{5d0ddda3a367ceb26fbaeca02e391c22} + \strng{bibnamehash}{5d0ddda3a367ceb26fbaeca02e391c22} + \strng{authorbibnamehash}{5d0ddda3a367ceb26fbaeca02e391c22} + \strng{authornamehash}{5d0ddda3a367ceb26fbaeca02e391c22} + \strng{authorfullhash}{5d0ddda3a367ceb26fbaeca02e391c22} + \field{sortinit}{S} + \field{sortinithash}{b164b07b29984b41daf1e85279fbc5ab} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{journaltitle}{Journal of Embedded Computing} + \field{number}{3} + \field{title}{Remote KVM-over-IP on the ASpeed AST2050} + \field{volume}{14} + \field{year}{2014} + \field{pages}{45\bibrangedash 49} + \range{pages}{5} + \endentry \entry{SridharanVilas2015MEiM}{article}{} \name{author}{7}{}{% {{hash=424e5d7c7305b93eade0897c378a833a}{% @@ -2207,6 +2292,94 @@ \field{pages}{297\bibrangedash 310} \range{pages}{14} \endentry + \entry{ast2050_architecture}{article}{} + \name{author}{1}{}{% + {{hash=5724d534bba82cf4cced0784f7ce038b}{% + family={Technology}, + familyi={T\bibinitperiod}, + given={ASpeed}, + giveni={A\bibinitperiod}}}% + } + \strng{namehash}{5724d534bba82cf4cced0784f7ce038b} + \strng{fullhash}{5724d534bba82cf4cced0784f7ce038b} + \strng{bibnamehash}{5724d534bba82cf4cced0784f7ce038b} + \strng{authorbibnamehash}{5724d534bba82cf4cced0784f7ce038b} + \strng{authornamehash}{5724d534bba82cf4cced0784f7ce038b} + \strng{authorfullhash}{5724d534bba82cf4cced0784f7ce038b} + \field{extraname}{1} + \field{sortinit}{T} + \field{sortinithash}{9af77f0292593c26bde9a56e688eaee9} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{journaltitle}{ASpeed Whitepaper} + \field{note}{Accessed: 2024-08-21} + \field{title}{ASpeed AST2050: ARM926EJ-S Based BMC Architecture} + \field{year}{2013} + \verb{urlraw} + \verb https://www.aspeedtech.com/products.php?fPath=20&rId=29 + \endverb + \verb{url} + \verb https://www.aspeedtech.com/products.php?fPath=20&rId=29 + \endverb + \endentry + \entry{ast2050_nic}{manual}{} + \name{author}{1}{}{% + {{hash=5724d534bba82cf4cced0784f7ce038b}{% + family={Technology}, + familyi={T\bibinitperiod}, + given={ASpeed}, + giveni={A\bibinitperiod}}}% + } + \strng{namehash}{5724d534bba82cf4cced0784f7ce038b} + \strng{fullhash}{5724d534bba82cf4cced0784f7ce038b} + \strng{bibnamehash}{5724d534bba82cf4cced0784f7ce038b} + \strng{authorbibnamehash}{5724d534bba82cf4cced0784f7ce038b} + \strng{authornamehash}{5724d534bba82cf4cced0784f7ce038b} + \strng{authorfullhash}{5724d534bba82cf4cced0784f7ce038b} + \field{extraname}{2} + \field{sortinit}{T} + \field{sortinithash}{9af77f0292593c26bde9a56e688eaee9} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{note}{Accessed: 2024-08-21} + \field{title}{ASpeed AST2050: Network Interface Controller for BMC} + \field{year}{2013} + \verb{urlraw} + \verb https://www.aspeedtech.com/products.php?fPath=20&rId=29 + \endverb + \verb{url} + \verb https://www.aspeedtech.com/products.php?fPath=20&rId=29 + \endverb + \endentry + \entry{ast2050_io}{manual}{} + \name{author}{1}{}{% + {{hash=5724d534bba82cf4cced0784f7ce038b}{% + family={Technology}, + familyi={T\bibinitperiod}, + given={ASpeed}, + giveni={A\bibinitperiod}}}% + } + \strng{namehash}{5724d534bba82cf4cced0784f7ce038b} + \strng{fullhash}{5724d534bba82cf4cced0784f7ce038b} + \strng{bibnamehash}{5724d534bba82cf4cced0784f7ce038b} + \strng{authorbibnamehash}{5724d534bba82cf4cced0784f7ce038b} + \strng{authornamehash}{5724d534bba82cf4cced0784f7ce038b} + \strng{authorfullhash}{5724d534bba82cf4cced0784f7ce038b} + \field{extraname}{3} + \field{sortinit}{T} + \field{sortinithash}{9af77f0292593c26bde9a56e688eaee9} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{note}{Accessed: 2024-08-21} + \field{title}{I/O Interfaces of the ASpeed AST2050} + \field{year}{2013} + \verb{urlraw} + \verb https://www.aspeedtech.com/products.php?fPath=20&rId=29 + \endverb + \verb{url} + \verb https://www.aspeedtech.com/products.php?fPath=20&rId=29 + \endverb + \endentry \entry{lip6_annuaire}{misc}{} \name{author}{1}{}{% {{hash=a220fc1da6562fa2e1e0bc05c201b485}{% @@ -2874,7 +3047,6 @@ \field{note}{[Online; accessed 8-May-2024]} \field{title}{OpenBMC --- {Wikipedia}{,} The Free Encyclopedia} \field{year}{2023} - \true{nocite} \verb{urlraw} \verb https://en.wikipedia.org/w/index.php?title=OpenBMC&oldid=1183698628 \endverb diff --git a/hardware_init_review.pdf b/hardware_init_review.pdf index 6cfe960..17ab101 100644 Binary files a/hardware_init_review.pdf and b/hardware_init_review.pdf differ diff --git a/hardware_init_review.tex b/hardware_init_review.tex index 1d28c39..4d95008 100644 --- a/hardware_init_review.tex +++ b/hardware_init_review.tex @@ -430,7 +430,8 @@ research and advocacy for free software-compatible hardware. support AMD Family 10h/15h series processors. Released in 2009, this mainboard was later awarded the \textit{Respects Your Freedom} (RYF) certification in March 2017, underscoring its commitment to fully free software compatibility - \cite{fsf_ryf}. \\ + \cite{fsf_ryf}. Indeed, this mainboard can be operated with a fully free + firmware such as GNU Boot \cite{gnuboot_status}. \\ This mainboard is equipped with robust hardware components designed to meet the demands of high-performance computing. It features 16 DDR3 DIMM @@ -445,7 +446,7 @@ research and advocacy for free software-compatible hardware. data-intensive tasks and network communication \cite{ASUS_kgpe_d16_manual}. Additionally, the board is equipped with various peripheral interfaces, including USB ports, audio outputs, and other I/O ports, ensuring compatibility - with a wide range of external devices. + with a wide range of external devices. \\ \begin{figure}[H] \centering @@ -631,9 +632,46 @@ research and advocacy for free software-compatible hardware. \section{Baseboard Management Controller} - TODO + The Baseboard Management Controller (BMC) on the KGPE-D16 motherboard, + specifically the ASpeed AST2050, plays a role in the server's + architecture by managing out-of-band communication and control of the hardware. + The AST2050 is based on an ARM926EJ-S processor, a low-power 32-bit ARM + architecture designed for embedded systems \cite{ast2050_architecture}. This + architecture is well-suited for BMCs due to its efficiency and capability to + handle multiple management tasks concurrently without significant resource + demands from the main system. \\ -\chapter{Key components in modern firmware} + The AST2050 features several key components that contribute to its functionality. + It includes an integrated VGA controller, which enables remote graphical + management through KVM-over-IP (Keyboard, Video, Mouse), a critical feature for + administrators who need to interact with the system remotely, including BIOS + updates and troubleshooting \cite{ast2050_kvm}. Additionally, the AST2050 + integrates a dedicated memory controller, which supports up to 256MB of DDR2 RAM. + This allows it to handle complex tasks and maintain responsiveness during + management operations \cite{ast2050_memory}. + The BMC also features a network interface controller (NIC) dedicated to + management traffic, ensuring that remote management does not interfere with the + primary network traffic of the server. This separation is vital for maintaining + secure and uninterrupted system management, especially in environments where + uptime is critical \cite{ast2050_nic}. + Another important architectural aspect of the AST2050 is its support for multiple + I/O interfaces, including I2C, GPIO, UART, and USB, which allow it to interface + with various sensors and peripherals on the motherboard \cite{ast2050_io}. This + versatility enables comprehensive monitoring of hardware health, such as + temperature sensors, fan speeds, and power supplies, all of which can be managed + and configured through the BMC. \\ + + When combined with OpenBMC \cite{openbmc_wiki}, a libre firmware that can be + run on the AST2050 thanks to Raptor Engineering \cite{raptor_engineering}, + the architecture of the BMC becomes even more powerful. OpenBMC takes + advantage of the AST2050's architecture, providing a flexible and + customizable environment that can be tailored to specific use cases. This + includes adding or modifying features related to security, logging, and network + management, all within the BMC's ARM architecture framework + \cite{openbmc_customization}. + + +\chapter{Key components in modern firmware [WIP]} \section{General structure of coreboot} @@ -896,7 +934,7 @@ research and advocacy for free software-compatible hardware. \textbf{ASUS KGPE-D16 Example}: The ASUS KGPE-D16 mainboard does not include the AMD Platform Security Processor (PSP) or the Intel ME. -\chapter{Memory initialization and training algorithms} +\chapter{Memory initialization and training algorithms [WIP]} \section{Importance of memory initialization} \begin{itemize} @@ -958,7 +996,7 @@ research and advocacy for free software-compatible hardware. \item \textbf{ASUS KGPE-D16 Example}: Specific case studies and firmware updates for the mainboard \end{itemize} -\chapter{Firmware and hardware virtualization} +\chapter{Firmware and hardware virtualization [WIP]} \section{Introduction to hardware virtualization} \begin{itemize} @@ -988,7 +1026,7 @@ research and advocacy for free software-compatible hardware. \item \textbf{ASUS KGPE-D16 Example}: Potential future firmware updates and their expected impact on the mainboard's virtualization capabilities \end{itemize} -\chapter*{Conclusion} +\chapter*{Conclusion [WIP]} \addcontentsline{toc}{chapter}{Conclusion} \section{Summary of key points} diff --git a/hardware_init_review.toc b/hardware_init_review.toc index 35886a7..020e287 100644 --- a/hardware_init_review.toc +++ b/hardware_init_review.toc @@ -1,38 +1,38 @@ \babel@toc {english}{}\relax -\contentsline {chapter}{Abstract}{4}{chapter*.1}% -\contentsline {chapter}{\numberline {1}Introduction to firmware and BIOS evolution}{5}{chapter.1}% -\contentsline {section}{\numberline {1.1}Historical context of BIOS}{5}{section.1.1}% -\contentsline {subsection}{\numberline {1.1.1}Definition and origin}{5}{subsection.1.1.1}% -\contentsline {subsection}{\numberline {1.1.2}Functionalities and limitations}{6}{subsection.1.1.2}% -\contentsline {section}{\numberline {1.2}Modern BIOS and UEFI}{7}{section.1.2}% -\contentsline {subsection}{\numberline {1.2.1}Transition from traditional BIOS to UEFI (Unified Extensible Firmware Interface)}{7}{subsection.1.2.1}% -\contentsline {subsection}{\numberline {1.2.2}An other way with \textit {coreboot}}{7}{subsection.1.2.2}% -\contentsline {section}{\numberline {1.3}Shift in firmware responsibilities}{9}{section.1.3}% -\contentsline {chapter}{\numberline {2}Characteristics of ASUS KGPE-D16 mainboard}{10}{chapter.2}% -\contentsline {section}{\numberline {2.1}Overview of ASUS KGPE-D16 hardware}{11}{section.2.1}% -\contentsline {section}{\numberline {2.2}Chipset}{12}{section.2.2}% -\contentsline {section}{\numberline {2.3}Processors}{14}{section.2.3}% -\contentsline {section}{\numberline {2.4}Baseboard Management Controller}{15}{section.2.4}% -\contentsline {chapter}{\numberline {3}Key components in modern firmware}{16}{chapter.3}% -\contentsline {section}{\numberline {3.1}General structure of coreboot}{16}{section.3.1}% -\contentsline {subsection}{\numberline {3.1.1}Bootblock stage}{17}{subsection.3.1.1}% -\contentsline {subsection}{\numberline {3.1.2}Romstage}{17}{subsection.3.1.2}% -\contentsline {subsection}{\numberline {3.1.3}Ramstage}{18}{subsection.3.1.3}% -\contentsline {subsection}{\numberline {3.1.4}Payload}{18}{subsection.3.1.4}% -\contentsline {section}{\numberline {3.2}Advanced Configuration and Power Interface}{18}{section.3.2}% -\contentsline {section}{\numberline {3.3}System Management Mode}{19}{section.3.3}% -\contentsline {section}{\numberline {3.4}AMD Platform Security Processor and Intel Management Engine}{19}{section.3.4}% -\contentsline {chapter}{\numberline {4}Memory initialization and training algorithms}{21}{chapter.4}% -\contentsline {section}{\numberline {4.1}Importance of memory initialization}{21}{section.4.1}% -\contentsline {section}{\numberline {4.2}Memory training algorithms}{21}{section.4.2}% -\contentsline {section}{\numberline {4.3}Practical examples}{21}{section.4.3}% -\contentsline {chapter}{\numberline {5}Firmware and hardware virtualization}{23}{chapter.5}% -\contentsline {section}{\numberline {5.1}Introduction to hardware virtualization}{23}{section.5.1}% -\contentsline {section}{\numberline {5.2}Role of BIOS/UEFI in virtualization}{23}{section.5.2}% -\contentsline {section}{\numberline {5.3}Security and freedom considerations}{23}{section.5.3}% -\contentsline {section}{\numberline {5.4}Future trends in firmware and virtualization}{23}{section.5.4}% -\contentsline {chapter}{Conclusion}{24}{chapter*.2}% -\contentsline {section}{\numberline {5.5}Summary of key points}{24}{section.5.5}% -\contentsline {section}{\numberline {5.6}Call for action}{24}{section.5.6}% -\contentsline {chapter}{Bibliography}{25}{section.5.6}% -\contentsline {chapter}{GNU Free Documentation License}{30}{chapter*.4}% +\contentsline {chapter}{Abstract}{5}{chapter*.1}% +\contentsline {chapter}{\numberline {1}Introduction to firmware and BIOS evolution}{6}{chapter.1}% +\contentsline {section}{\numberline {1.1}Historical context of BIOS}{6}{section.1.1}% +\contentsline {subsection}{\numberline {1.1.1}Definition and origin}{6}{subsection.1.1.1}% +\contentsline {subsection}{\numberline {1.1.2}Functionalities and limitations}{7}{subsection.1.1.2}% +\contentsline {section}{\numberline {1.2}Modern BIOS and UEFI}{8}{section.1.2}% +\contentsline {subsection}{\numberline {1.2.1}Transition from traditional BIOS to UEFI (Unified Extensible Firmware Interface)}{8}{subsection.1.2.1}% +\contentsline {subsection}{\numberline {1.2.2}An other way with \textit {coreboot}}{8}{subsection.1.2.2}% +\contentsline {section}{\numberline {1.3}Shift in firmware responsibilities}{10}{section.1.3}% +\contentsline {chapter}{\numberline {2}Characteristics of ASUS KGPE-D16 mainboard}{11}{chapter.2}% +\contentsline {section}{\numberline {2.1}Overview of ASUS KGPE-D16 hardware}{12}{section.2.1}% +\contentsline {section}{\numberline {2.2}Chipset}{13}{section.2.2}% +\contentsline {section}{\numberline {2.3}Processors}{15}{section.2.3}% +\contentsline {section}{\numberline {2.4}Baseboard Management Controller}{16}{section.2.4}% +\contentsline {chapter}{\numberline {3}Key components in modern firmware [WIP]}{18}{chapter.3}% +\contentsline {section}{\numberline {3.1}General structure of coreboot}{18}{section.3.1}% +\contentsline {subsection}{\numberline {3.1.1}Bootblock stage}{19}{subsection.3.1.1}% +\contentsline {subsection}{\numberline {3.1.2}Romstage}{19}{subsection.3.1.2}% +\contentsline {subsection}{\numberline {3.1.3}Ramstage}{20}{subsection.3.1.3}% +\contentsline {subsection}{\numberline {3.1.4}Payload}{20}{subsection.3.1.4}% +\contentsline {section}{\numberline {3.2}Advanced Configuration and Power Interface}{20}{section.3.2}% +\contentsline {section}{\numberline {3.3}System Management Mode}{21}{section.3.3}% +\contentsline {section}{\numberline {3.4}AMD Platform Security Processor and Intel Management Engine}{21}{section.3.4}% +\contentsline {chapter}{\numberline {4}Memory initialization and training algorithms [WIP]}{23}{chapter.4}% +\contentsline {section}{\numberline {4.1}Importance of memory initialization}{23}{section.4.1}% +\contentsline {section}{\numberline {4.2}Memory training algorithms}{23}{section.4.2}% +\contentsline {section}{\numberline {4.3}Practical examples}{24}{section.4.3}% +\contentsline {chapter}{\numberline {5}Firmware and hardware virtualization [WIP]}{25}{chapter.5}% +\contentsline {section}{\numberline {5.1}Introduction to hardware virtualization}{25}{section.5.1}% +\contentsline {section}{\numberline {5.2}Role of BIOS/UEFI in virtualization}{25}{section.5.2}% +\contentsline {section}{\numberline {5.3}Security and freedom considerations}{25}{section.5.3}% +\contentsline {section}{\numberline {5.4}Future trends in firmware and virtualization}{25}{section.5.4}% +\contentsline {chapter}{Conclusion}{26}{chapter*.2}% +\contentsline {section}{\numberline {5.5}Summary of key points}{26}{section.5.5}% +\contentsline {section}{\numberline {5.6}Call for action}{26}{section.5.6}% +\contentsline {chapter}{Bibliography}{27}{section.5.6}% +\contentsline {chapter}{GNU Free Documentation License}{32}{chapter*.4}%