diff --git a/bibliographie.bib b/bibliographie.bib index 3f8ab23..ff936b9 100644 --- a/bibliographie.bib +++ b/bibliographie.bib @@ -89,14 +89,14 @@ journal = {Queue}, doi = {10.1145/2508834.2513149} } -@misc{micron_ddr3, +@manual{micron_ddr3, author = {Micron Technology Inc}, year = {2008}, number = {TN-41-02}, title = {Technical Note: DDR3 ZQ Calibration} } -@misc{samsung_ddr3, +@manual{samsung_ddr3, author = {Samsung Electronics Co. Ltd}, year = {2011}, month = {11}, @@ -253,27 +253,7 @@ note = "[Online; accessed 8-May-2024]" note = {Accessed: 2024-07-05} } -@article{memory_training, - author = {Author Names}, - title = {Title of the Paper on Memory Training Algorithms}, - journal = {Journal Name}, - year = {Year}, - volume = {Volume}, - number = {Number}, - pages = {Pages} -} - -@article{virtualization_firmware, - author = {Author Names}, - title = {Title of the Paper on Hardware Virtualization and Firmware}, - journal = {Journal Name}, - year = {Year}, - volume = {Volume}, - number = {Number}, - pages = {Pages} -} - -@misc{asus_kgpe_d16_manual, +@manual{asus_kgpe_d16_manual, author = {Asus}, title = {Asus KGPE-D16 Mainboard Documentation and User Manuals}, howpublished = {\url{https://www.asus.com/Commercial-Servers-Workstations/KGPE-D16/HelpDesk_Manual/}}, @@ -301,13 +281,6 @@ note = "[Online; accessed 8-May-2024]" year = 2024 } -@misc{computer_history_museum, - author = {Computer History Museum}, - title = {The Evolution of the BIOS}, - howpublished = {\url{https://computerhistory.org/}}, - year = 2024 -} - @book{rosenberg1994open, title={Open architecture computer systems}, author={Rosenberg, Ronald H}, @@ -344,13 +317,6 @@ note = "[Online; accessed 8-May-2024]" howpublished = {\url{https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/uefi-firmware}}, } -@misc{smith_2017, - author = {Smith, R.}, - title = {UEFI vs. BIOS: What’s the Difference?}, - year = {2017}, - howpublished = {\url{https://www.techradar.com/news/uefi-vs-bios-whats-the-difference}}, -} - @misc{anderson_2018, author = {Anderson, T.}, title = {BIOS vs. UEFI: Understanding the Modern Boot Environment}, @@ -435,7 +401,7 @@ note = "[Online; accessed 8-May-2024]" @article{coreboot_challenges, author = {Minnich, R. and Hendricks, E.}, - title = {Challenges and Progress in Coreboot Development}, + title = {Challenges and Progress in coreboot Development}, journal = {Journal of Open Source Software}, year = {2018}, volume = {3}, @@ -449,4 +415,496 @@ note = "[Online; accessed 8-May-2024]" title = {Frequently Asked Questions}, howpublished = {\url{https://www.gnu.org/software/gnuboot/web/faq.html}}, note = {Accessed: 2024-07-23} +} + +@book{intel_acpi_spec, + author = {Intel Corporation}, + title = {Advanced Configuration and Power Interface (ACPI) Specification}, + year = {1996}, + publisher = {Intel Corporation}, + url = {https://uefi.org/specifications} +} + +@article{acpi_os_support, + author = {Michael Gschwind}, + title = {Advanced Configuration and Power Interface: The Operating System Perspective}, + journal = {IEEE Micro}, + year = {2000}, + volume = {20}, + pages = {82-89}, + doi = {10.1109/40.888702} +} + +@book{uefi_smm_security, + author = {Ronald D. Krebs and Vincent Zimmer and Suresh Marisetty}, + title = {Beyond BIOS: Developing with the Unified Extensible Firmware Interface}, + edition = {3rd}, + year = {2017}, + publisher = {Intel Press}, + isbn = {978-0974364906} +} + +@inproceedings{amd_psp_overview, + author = {David Kaplan and Jeremy Powell and Tom Woller}, + title = {AMD Memory Encryption}, + booktitle = {Architectural Support for Programming Languages and Operating Systems}, + year = {2016}, + pages = {149-160}, + doi = {10.1145/2851141.2851148} +} + +@techreport{intel_csme, + author = {Intel Corporation}, + title = {Intel Converged Security and Management Engine (CSME) Security White Paper}, + year = {2020}, + url = {https://www.intel.com/content/dam/www/public/us/en/security-advisory/documents/intel-csme-security-white-paper.pdf} +} + +@article{heasman2007, + author = {John Heasman}, + title = {Implementing and Detecting an ACPI BIOS Rootkit}, + journal = {Black Hat USA}, + year = {2007}, + url = {https://www.blackhat.com/presentations/bh-usa-07/Heasman/Presentation/bh-usa-07-heasman.pdf} +} + +@article{domas2015, + author = {Christopher Domas}, + title = {The Memory Sinkhole - Unleashing an x86 Design Flaw Allowing Universal Privilege Escalation}, + journal = {Black Hat USA}, + year = {2015}, + url = {https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation-wp.pdf} +} + +@article{offsec_bios_smm, + author = {Corey Kallenberg and Xeno Kovah}, + title = {BIOS and SMM Internals}, + year = {2014}, + url = {https://opensecuritytraining.info/IntroBIOS_files/Day1_07_Advanced%20x86%20-%20BIOS%20and%20SMM%20Internals%20-%20SMM.pdf} +} + +@techreport{cyber_smm_hack, + author = {Olivier Levillain and Aurelien Francillon and Yanick Fratantonio and Davide Balzarotti}, + title = {How to Protect the BIOS and its Secrets}, + institution = {ANSSI, Eurecom}, + year = {2011}, + url = {https://cyber.gouv.fr/sites/default/files/IMG/pdf/Cansec_final.pdf} +} + +@article{blackhat_me_hack, + author = {Maxim Goryachy and Mark Ermolov}, + title = {How to Hack a Turned Off Computer, or Running Unsigned Code in Intel Management Engine}, + journal = {Black Hat Europe}, + year = {2017}, + pages = {1-23}, + url = {https://www.blackhat.com/docs/eu-17/materials/eu-17-Goryachy-How-To-Hack-A-Turned-Off-Computer-Or-Running-Unsigned-Code-In-Intel-Management-Engine-wp.pdf} +} + +@manual{acpi_programming, + title = {ACPI Component Architecture Programmer Reference}, + author = {ACPICA Project}, + year = {2017}, + url = {https://acpica.org/documentation}, + note = {Accessed: 2024-08-03} +} + +@manual{coreboot_docs, + title = {coreboot Documentation}, + author = {coreboot Project}, + year = {2023}, + url = {https://doc.coreboot.org/} +} + +@article{minnich_coreboot, + author = {Ron Minnich and Stefan Reinauer and Patrick Georgi}, + title = {coreboot: Open-Source Firmware Platform}, + journal = {Google Research}, + year = {2017}, + url = {https://research.google/pubs/pub45424/} +} + +@inproceedings{minnich_status, + author = {Ron Minnich}, + title = {coreboot: Status and some history}, + year = {2006}, +} + +@techreport{intel_smm, + author = {Intel Corporation}, + title = {System Management Mode}, + year = {2016}, + url = {https://www.intel.com/content/www/us/en/developer/articles/technical/system-management-mode.html} +} + +@article{coprocessor_smm_monitoring, + author = {Aurelien Francillon and others}, + title = {Co-processor-based Behavior Monitoring: Application to the Detection of Attacks Against the System Management Mode}, + journal = {arXiv}, + year = {2018}, + url = {https://arxiv.org/abs/1803.02700} +} + +@inproceedings{brown2003linuxbios, + title = {LinuxBIOS as an Open-Source Firmware Alternative}, + author = {R. E. Brown and others}, + booktitle = {Proceedings of the 2003 Linux Symposium}, + year = {2003} +} + +@inproceedings{reinauer2008coreboot, + title = {The coreboot Open Source BIOS - A Review}, + author = {Stefan Reinauer and others}, + booktitle = {Usenix Annual Technical Conference}, + year = {2008} +} + +@techreport{mohr2012comparative, + title = {A Comparative Analysis of Bootloaders}, + author = {Benjamin Mohr}, + institution = {University of Freiburg}, + year = {2012} +} + +@article{HaiYa2024Awah, +% abstract = {This paper presents a wide-frequency and high-precision ZQ calibration circuit for NAND Flash memory. To achieve high-precision impedance calibration within the wide frequency range of NAND Flash memory, the proposed ZQ calibration circuit adopts dynamic comparator with offset voltage compensation to accurately control the equivalent impedance of driver. And to ensure that the offset voltage of comparator can be accurately compensated in a wide frequency range, the offset voltage compensation circuit is controlled by a charge pump whose charging and discharging step time can be adjusted based on operating frequency range. The proposed circuit is fabricated in 130 nm CMOS process. In the frequency range of 1 MHz to 200 MHz, the Monte-Carlo analysis results show that the standard deviation of offset voltage is within 0.18 mV and the standard deviation of targeting calibrated impedance on 300 ohm is within 3.5 ohm. And the chip testing results show that the proposed ZQ calibration circuit can achieve 1.5% calibration accuracy.}, +author = {Hai, Ya and Liu, Fei and Wang, Yongshan and Fu, Liyin and Huo, Jian}, +copyright = {2023}, +issn = {1879-2391}, +journal = {Microelectronics}, +language = {eng}, +pages = {106051-}, +title = {A wide-frequency and high-precision ZQ calibration circuit for NAND Flash memory}, +volume = {143}, +year = {2024}, +publisher = {Elsevier Ltd} +} + +@inproceedings{pearson2014, + title = {The World Beyond x86}, + author = {Timothy Pearson}, + year = {2014} +} + +@inproceedings{altera2008, + title = {DDR3 SDRAM Memory Interface Termination and Layout Guidelines}, + author = {Altera®}, + year = {2008}, + number = {AN-520-1.0} +} + +@article{LiHuiyong2014RRoD, +% abstract = {The signal integrity of the circuit, as one of the important design issues in high-speed digital system, is usually seriously affected by the signal reflection due to impedance mismatch in the DDR3 bus. In this paper, a novel optimization method is proposed to optimize impedance mismatch and reduce the signal refection. Specifically, by applying the via parasitic, an equivalent model of DDR3 high-speed signal transmission, which bases on the match between the on-die-termination (ODT) value of DDR3 and the characteristic impedance of the transmission line, is established. Additionally, an improved particle swarm optimization algorithm with adaptive perturbation is presented to solve the impedance mismatch problem (IPSO-IMp) based on the above model. The algorithm dynamically judges particles’ state and introduces perturbation strategy for local aggregation, from which the local optimum is avoided and the ability of optimization-searching is activated. IPSO-IMp achieves higher accuracy than the standard algorithm, and the speed increases nearly 33% as well. Finally, the simulation results verify that the solution obviously decreases the signal reflection, with the signal transmission quality increasing by 1.3 dB compared with the existing method.}, +author = {Li, Huiyong and Jiang, Hongxu and Li, Bo and Duan, Miyi}, +address = {United States}, +copyright = {Copyright © 2014 Huiyong Li et al.}, +issn = {2356-6140}, +journal = {TheScientificWorld}, +keywords = {Algorithms ; Buses ; Efficiency ; Experiments ; Mathematical models ; Mathematical optimization ; Motor vehicles ; Properties ; Reading ; Signals and signaling}, +language = {eng}, +pages = {257972-11}, +title = {Reflection Reduction on DDR3 High-Speed Bus by Improved PSO}, +volume = {2014}, +year = {2014}, +publisher = {Hindawi Publishing Corporation} +} + + +@article{ChengKaixing2021TOWo, +% abstract = {As we enter the 5G (5th-Generation) era, the amount of information and data has become increasingly tremendous. Therefore, electronic circuits need to have higher chip density, faster operating speed and better signal quality of transmission. As the carrier of electronic components, the design difficulty of high-speed PCB (Printed Circuit Board) is also increasing. Equal-length wiring is an essential part of PCB design. But now, it can no longer meet the needs of designers. Accordingly, in view of the shortcomings of the traditional equal-length wiring, this article proposes two optimization ways: the ”spiral wiring” way and the ”double spiral wiring” way. Based on the theoretical analysis of the transmission lines, the two optimization ways take the three aspects of optimizing the layout and wiring space, suppressing crosstalk and reducing reflection as the main points to optimize the design. Eventually, this article performs simulation and verification of schematic diagram and PCB of the optimal design by using HyperLynx simulation software. The simulation results show that these two ways not only improve the flexibility of the transmission line layout, but also improve the signal integrity of the transmission lines. Of course, this also proves the feasibility and reliability of the two optimized designs.}, +author = {Cheng, Kaixing and Luo, Zhongqiang and Xiong, Xingzhong and Wei, Xiaohan}, +address = {Warsaw}, +copyright = {2021. This work is licensed under https://creativecommons.org/licenses/by-sa/4.0/ (the “License”). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License.}, +issn = {2081-8491}, +journal = {International Journal of Electronics and Telecommunications}, +keywords = {Crosstalk ; Design ; Electric lines ; Electronic circuits ; Optimal designs (Statistics) ; Printed circuits ; Telecommunication lines}, +language = {eng}, +number = {3}, +pages = {385-394}, +title = {Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity}, +volume = {67}, +year = {2021}, +publisher = {Polish Academy of Sciences} +} + +@article{ErmolovMarkM.2022Uxit, +% abstract = {The purpose of this study was to uncover previously unknown vulnerabilities in Intel CPUs caused by implementation errors or backdoors embedded in system firmware, applications, and hardware. The authors have discovered the Red Unlocked debugging mode which allows microcode to be extracted from Intel Atom processors. Using this debugging mode, the internal microcode structure and the implementation of x86 instructions have been examined, and two undocumented x86 instructions were found. These undocumented x86 instructions, udbgrd and udbgwr, can read and write microarchitectural data. These instructions are assumed to be intended for Intel engineers to debug the CPU microarchitecture. However, their existence poses a cybersecurity threat: there is a working demonstration available in the public domain on how to activate the Red Unlock mode for one of the current Intel platforms. This paper presents the analysis of the udbgrd and udbgwr instructions and explains the conditions under which they can be used on commonly available platforms. This kind of research can be used to develop methods, tools, and solutions to ensure information security of systems and networks by countering threats that arise from newly identified vulnerabilities stemming from implementation defects or backdoors in system firmware, applications, and hardware.}, +author = {Ermolov, Mark M. and Sklyarov, Dmitry V. and Goryachy, Maxim S.}, +issn = {2074-7128}, +journal = {Bezopasnostʹ informatÍ¡s︡ionnykh tekhnologiÄ­}, +language = {eng}, +number = {4}, +pages = {27-41}, +title = {Undocumented x86 instructions to control the CPU at the microarchitecture level in modern INTEL processors}, +volume = {29}, +year = {2022}, +publisher = {Joint Stock Company "Experimental Scientific and Production Association SPELS} +} + +@article{EmbletonShawn2013Sran, +% abstract = {The emergence of hardware virtualization technology has led to the development of OS independent malware such as the virtual machine‐based rootkits (VMBRs). In this paper, we draw attention to a different but related threat that exists on many commodity systems in operation today: The system management Mode based rootkit (SMBR). System Management mode (SMM) is a relatively obscure mode on Intel processors used for low‐level hardware control. It has its own private memory space and execution environment which is generally invisible to code running outside (e.g., the Operating System). Furthermore, SMM code is completely non‐preemptible, lacks any concept of privilege level, and is immune to memory protection mechanisms. These features make it a potentially attractive home for stealthy rootkits used for high‐profile targeted attacks. In this paper, we present our development of a proof of concept SMM rootkit. In it, we explore the potential of system management mode for malicious use by implementing a chipset level keylogger and a network backdoor capable of directly interacting with the network card to send logged keystrokes to a remote machine via UDP and receive remote command packets stealthily. By modifying and reflashing the BIOS, the SMM rootkit can install itself on a computer even if the computer has originally locked its SMM. The rootkit hides its memory footprint and requires no changes to the existing operating system. It is compared and contrasted with VMBRs. Finally, techniques to defend against these threats are explored. By taking an offensive perspective we hope to help security researchers better understand the depth and scope of the problems posed by an emerging class of OS independent malware. Copyright © 2009 John Wiley & Sons, Ltd. This paper presents a proof‐of‐concept SMM rootkit, which explores the potential vulnerability of the low‐level Intel processors' System Management Mode so that it cannot be detected by security software running based on the Operating System. To illustrate the capability of a stealthy SMM rootkit, we implement a chipset‐level keylogger and a network backdoor capable of directly interacting with the network card to send logged keystrokes to a remote machine via UDP and receive remote command packets stealthily.}, +author = {Embleton, Shawn and Sparks, Sherri and Zou, Cliff C.}, +address = {London}, +copyright = {Copyright © 2010 John Wiley & Sons, Ltd.}, +issn = {1939-0114}, +journal = {Security and communication networks}, +language = {eng}, +number = {12}, +pages = {1590-1605}, +title = {SMM rootkit: a new breed of OS independent malware}, +volume = {6}, +year = {2013}, +publisher = {Blackwell Publishing Ltd} +} + +@article{WaqarMuhammad2021DDCF, +% abstract = {This paper shows that an intermittent AC coupling defect occurring in a DDR4 data channel will cause more intermittent errors in DDR4, compared to such defect in DDR3. The intermittent AC coupling defect occurs due to intermittent fracture in DDR4 package solder ball. The defect causes DC offset in DDR4, which shifts the data signal or data eye and results in DDR4 data channel failure. The DC offset occurs due to the asymmetric nature of pseudo open drain termination scheme. DDR4 data channel response is compared with DDR3 channel. It is shown that pseudo random binary sequence (PRBS) pattern will always cause failure for DDR4, but PRBS will only cause failure in DDR3 if the sequence of consecutive 0's or 1's in PRBS pattern is long enough to cause threshold violation. As a result there will be more intermittent errors in DDR4 compared to DDR3. The defect due to fracture in solder ball is modelled by an AC coupling capacitor. A 1nF AC coupling capacitor corresponding to a solder ball fracture of height about 1nm is used to show the difference between DDR4 and DDR3 response.}, +author = {Waqar, Muhammad and Bak, Geunyong and Kwon, Junhyeong and Baeg, Sanghyeon}, +address = {Piscataway}, +copyright = {Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021}, +issn = {2169-3536}, +journal = {IEEE access}, +keywords = {Capacitors ; Couplings ; Printed circuits}, +language = {eng}, +pages = {63002-63011}, +title = {DDR4 Data Channel Failure Due to DC Offset Caused by Intermittent Solder Ball Fracture in FBGA Package}, +volume = {9}, +year = {2021}, +publisher = {IEEE} +} + +@inproceedings{BashunVladimir2013Tytb, +% abstract = {Unified Extensible Firmware Interface (UEFI) is a software interface between an operating system and platform firmware designed to replace a traditional BIOS. In general, UEFI has many technical advantages over BIOS (pre-OS environment, boot and run-time services, CPU-independent drivers etc.) including also powerful security mechanisms (e.g. secure boot, update, etc.). They are aimed to provide platform integrity, be root of trust of security architecture, control all stages of boot process until it pass control to authenticated OS kernel. From the other side UEFI technology is the focus of many new potential threats and exploits and presents new vulnerabilities that must be managed. The main goal of this research is to provide analysis of the UEFI security issues, find the point and source of the security problems and classify them. The paper describes the architectural and implementation troubles of UEFI which lead to threats, vulnerabilities and attacks. It also includes extensive review of the previous research activities in this area and the results of our own experiments. As the result of the work some recommendation about how to make this young technology more safe and secure are provided.}, +author = {Bashun, Vladimir and Sergeev, Anton and Minchenkov, Victor and Yakovlev, Alexandr}, +booktitle = {14th Conference of Open Innovation Association FRUCT}, +isbn = {1479949779}, +issn = {2305-7254}, +keywords = {Hardware ; Microprogramming}, +language = {eng}, +number = {14}, +pages = {16-24}, +title = {Too young to be secure: Analysis of UEFI threats and vulnerabilities}, +volume = {232}, +year = {2013}, +publisher = {FRUCT Oy} +} + +@article{AlexanderOgolyuk2017UBaI, +% abstract = {We describe principles and implementation details of UEFI BIOS attacks and vulnerabilities, suggesting the possible security enhancement approaches. We describe the hidden Intel Management Engine implementation details and possible consequences of its security possible discredit. Described breaches in UEFI and Intel Management Engine could possibly lead to the invention of "invulnerable" malicious applications. We highlight the base principles and actual state of Management Engine (which is a part of UEFI BIOS firmware) and its attack vectors using reverse engineering techniques.}, +author = {Alexander Ogolyuk and Andrey Sheglov and Konstantin Sheglov}, +issn = {2305-7254}, +journal = {Proceedings of the XXth Conference of Open Innovations Association FRUCT}, +language = {eng}, +number = {20}, +pages = {657-662}, +title = {UEFI BIOS and Intel Management Engine Attack Vectors and Vulnerabilities}, +volume = {776}, +year = {2017}, +publisher = {FRUCT} +} + +@inproceedings{ChevalierRonny2017CBMA, +% abstract = {Highly privileged software, such as firmware, is an attractive target for attackers. Thus, BIOS vendors use cryptographic signatures to ensure firmware integrity at boot time. Nevertheless, such protection does not prevent an attacker from exploiting vulnerabilities at runtime. To detect such attacks, we propose an event-based behavior monitoring approach that relies on an isolated co-processor. We instrument the code executed on the main CPU to send information about its behavior to the monitor. This information helps to resolve the semantic gap issue. Our approach does not depend on a specific model of the behavior nor on a specific target. We apply this approach to detect attacks targeting the System Management Mode (SMM), a highly privileged x86 execution mode executing firmware code at runtime. We model the behavior of SMM using invariants of its control-flow and relevant CPU registers (CR3 and SMBASE). We instrument two open-source firmware implementations: EDK II and coreboot. We evaluate the ability of our approach to detect state-of-the-art attacks and its runtime execution overhead by simulating an x86 system coupled with an ARM Cortex A5 co-processor. The results show that our solution detects intrusions from the state of the art, without any false positives, while remaining acceptable in terms of performance overhead in the context of the SMM (i.e., less than the 150 µs threshold defined by Intel).}, +author = {Chevalier, Ronny and Villatel, Maugan and Plaquin, David and Hiet, Guillaume}, +copyright = {Distributed under a Creative Commons Attribution 4.0 International License}, +keywords = {Computer science}, +language = {eng}, +pages = {399-411}, +title = {Co-processor-based Behavior Monitoring: Application to the Detection of Attacks Against the System Management Mode}, +volume = {2017}, +year = {2017}, +publisher = {ACM} +} + +@article{YiJinhui2021DoDS, +% abstract = {In order to flexibly adjust the frame delay of real-time image acquisition by high-resolution cameras, which is based on optical fiber communication protocol, and facilitate subsequent control, this article uses MT41J128M16JT-125IT DDR3 SDRAM of Mircon company to cache image data. And based on the MIG controller that comes with Xilinx Vivado development tool for continuous read and write control, the results show that when the camera system is designed at 2fps and the system clock is 50Mhz, the system data bandwidth is 2.2Gbps. The selected DDR3 chip has a bandwidth of 6.25Gbps, which can meet the real-time transmission requirements of the design system.}, +author = {Yi, Jinhui and Wang, Mingfu and Bai, Lidong}, +address = {Bristol}, +copyright = {2021. This work is published under http://creativecommons.org/licenses/by/3.0/ (the “License”). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License.}, +issn = {1742-6588}, +journal = {Journal of physics. Conference series}, +keywords = {Cameras ; Optical fibers ; Physics ; Realtime . . .}, +language = {eng}, +number = {1}, +pages = {12046-}, +title = {Design of DDR3 SDRAM read-write controller based on FPGA}, +volume = {1846}, +year = {2021}, +publisher = {IOP Publishing} +} + +@article{VersenM.2020Rhaa, +% abstract = {A DDR3 SDRAM test setup implemented on the Griffin III test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests for different manufacturing technologies. The row hammer effect is depending on the number of stress activation cycles. The analysis is extended to an avoidance scheme with refreshes similar to the Target Row Refresh scheme for the DDR4 SDRAM technology.}, +author = {Versen, M. and Ernst, W.}, +copyright = {2020}, +issn = {0026-2714}, +journal = {Microelectronics and reliability}, +language = {eng}, +pages = {113744-}, +title = {Row hammer avoidance analysis of DDR3 SDRAM}, +volume = {114}, +year = {2020}, +publisher = {Elsevier Ltd} +} + +@article{WangDong2019AIUb, +% abstract = {The Unified Extensible Firmware Interface (UEFI) is a software interface between an operating system and platform firmware designed to replace a traditional BIOS. In this paper, we evaluated the security mechanisms used to protected SPI Flash, and then analyzed the attack surface presented by those security mechanisms. Intel provides several registers in its chipset relevant to locking down the SPI Flash chip that contains the UEFI in order to prevent arbitrary writes. Since these registers implement their functions through the system management mode, the main attack surface is concentrated in the system management mode. In this paper, we propose an attack vector for the system management mode, which uses the method of cache poisoning to attack the system management mode and destroy the protection mechanism of SPI Flash. This method can overcome the limitations for the traditional attacks. Experimental results proved that this kind of attack can arbitrarily write to the UEFI.}, +author = {Wang, Dong and Dong, Wei Yu}, +address = {Bristol}, +copyright = {Published under licence by IOP Publishing Ltd}, +issn = {1742-6588}, +journal = {Journal of physics. Conference series}, +keywords = {Alliances ; Integrated circuits ; Poisoning}, +language = {eng}, +number = {4}, +pages = {42072-}, +title = {Attacking Intel UEFI by Using Cache Poisoning}, +volume = {1187}, +year = {2019}, +publisher = {IOP Publishing} +} + +@article{SridharanVilas2015MEiM, +% abstract = {Several recent publications have shown that hardware faults in the memory subsystem are commonplace. These faults are predicted to become more frequent in future systems that contain orders of magnitude more DRAM and SRAM than found in current memory subsystems. These memory subsystems will need to provide resilience techniques to tolerate these faults when deployed in high-performance computing systems and data centers containing tens of thousands of nodes. Therefore, it is critical to understand the efficacy of current hardware resilience techniques to determine whether they will be suitable for future systems. In this paper, we present a study of DRAM and SRAM faults and errors from the field. We use data from two leadership-class high-performance computer systems to analyze the reliability impact of hardware resilience schemes that are deployed in current systems. Our study has several key findings about the efficacy of many currently deployed reliability techniques such as DRAM ECC, DDR address/command parity, and SRAM ECC and parity. We also perform a methodological study, and find that counting errors instead of faults, a common practice among researchers and data center operators, can lead to incorrect conclusions about system reliability. Finally, we use our data to project the needs of future large-scale systems. We find that SRAM faults are unlikely to pose a significantly larger reliability threat in the future, while DRAM faults will be a major concern and stronger DRAM resilience schemes will be needed to maintain acceptable failure rates similar to those found on today's systems.}, +author = {Sridharan, Vilas and DeBardeleben, Nathan and Blanchard, Sean and Ferreira, Kurt B. and Stearley, Jon and Shalf, John and Gurumurthi, Sudhanva}, +issn = {0163-5964}, +journal = {Computer architecture news}, +language = {eng}, +number = {1}, +pages = {297-310}, +title = {Memory Errors in Modern Systems: The Good, The Bad, and The Ugly}, +volume = {43}, +year = {2015} +} + +@book{freiberger2000fire, + title={Fire in the Valley: The Birth and Death of the Personal Computer}, + author={Freiberger, Paul and Swaine, Michael}, + year={2000}, + publisher={McGraw-Hill} +} + +@misc{shustek2016kildall, + title={In His Own Words: Gary Kildall}, + author={Leonard J. Shustek}, + year={2016}, + howpublished={Computer History Museum Blog}, + url={https://computerhistory.org/blog/in-his-own-words-gary-kildall/}, + note={Accessed: August 16, 2024} +} + +@misc{wiki_bios, +author = "{Wikipedia contributors}", +title = "BIOS --- {Wikipedia}{,} The Free Encyclopedia", +year = "2024", +howpublished = "\url{https://en.wikipedia.org/w/index.php?title=BIOS&oldid=1240397019}", +note = "[Online; accessed 16-August-2024]" +} + +@misc{fsf_ryf, + author = {{Free Software Foundation}}, + title = {Respects Your Freedom (RYF) Certification}, + year = 2017, + url = {https://ryf.fsf.org/products/VikingsD16}, + note = {Accessed: 2024-08-17} +} + +@misc{vikings, + author = {{Vikings GmbH}}, + title = {Vikings Hardware Recommendations for KGPE-D16}, + url = {https://wiki.vikings.net/KGPE-D16}, + note = {Accessed: 2024-08-17} +} + +@misc{amd_chipsets, + author = {{Advanced Micro Devices (AMD)}}, + title = {AMD Embedded Chipsets: SR5690 and SP5100}, + url = {https://www.amd.com/en/products/embedded-chipsets}, + note = {Accessed: 2024-08-17} +} + +@manual{winbond, + title = {WINBOND W83667HG-A Datasheet}, + author = {{Winbond Electronics Corporation}}, + url = {https://www.winbond.com/}, + note = {Accessed: 2024-08-17} +} + +@manual{nuvoton, + title = {Nuvoton W83795G/ADG Hardware Monitor Datasheet}, + author = {{Nuvoton Technology Corporation}}, + url = {https://www.nuvoton.com/}, + note = {Accessed: 2024-08-17} +} + +@manual{amd_bsp, +title = {AMD Family 15h Models 30h-3Fh Processors BIOS and Kernel Developer's Guide}, +author = {{Advanced Micro Devices (AMD)}}, +year = 2014, +url = {https://www.amd.com/system/files/TechDocs/48751_15h_Mod_30h-3Fh_BKDG.pdf}, +note = {Accessed: 2024-08-17} +} + +@misc{northbridge_wiki, +author = "{Wikipedia contributors}", +title = "Northbridge (computing) --- {Wikipedia}{,} The Free Encyclopedia", +year = "2024", +howpublished = "\url{https://en.wikipedia.org/w/index.php?title=Northbridge_(computing)&oldid=1231509957}", +note = "[Online; accessed 17-August-2024]" +} + +@misc{southbridge_wiki, +author = "{Wikipedia contributors}", +title = "Southbridge (computing) --- {Wikipedia}{,} The Free Encyclopedia", +year = "2024", +howpublished = "\url{https://en.wikipedia.org/w/index.php?title=Southbridge_(computing)&oldid=1239483618}", +note = "[Online; accessed 17-August-2024]" +} + +@inproceedings{coreboot_fsf, + author = {Ward Vandewege}, + title = {Coreboot: the view from the FSF}, + year = {2008}, +} + +@manual{amd_6200, + title = {AMD Opteron 6200 Series Processor}, + author = {{AMD}}, + year = 2011, + note = {Available at AMD Developer Central}, + url = {https://developer.amd.com/} +} + +@article{anandtech_bulldozer, + author = {Anand Lal Shimpi}, + title = {The Bulldozer Review: AMD FX-8150 Tested}, + journal = {AnandTech}, + year = 2011, + url = {https://www.anandtech.com/show/4955/the-bulldozer-review-amd-fx8150-tested} +} + +@article{hill_impact_caching, + author = {Hill, M. D. and Marty, M. R.}, + title = {The Impact of Caching on Multicore Performance}, + journal = {Communications of the ACM}, + volume = {51}, + number = {12}, + pages = {48--54}, + year = {2008}, + publisher = {ACM} +} + +@manual{amd_ddr3_guide, + title = {AMD DDR3 Memory Controller: Technical Overview}, + author = {{AMD}}, + year = 2011, + note = {Available at AMD Developer Central}, + url = {https://developer.amd.com/} +} + +@manual{amd_ht_guide, + title = {HyperTransport Technology: Technical Overview}, + author = {{AMD}}, + year = 2011, + note = {Available at AMD Developer Central}, + url = {https://developer.amd.com/} } \ No newline at end of file diff --git a/hardware_init_review..bbl b/hardware_init_review..bbl deleted file mode 100644 index e69de29..0000000 diff --git a/hardware_init_review.bbl b/hardware_init_review.bbl index b137f83..77e40b1 100644 --- a/hardware_init_review.bbl +++ b/hardware_init_review.bbl @@ -67,7 +67,81 @@ \field{title}{ACPI Specification} \true{nocite} \endentry - \entry{amd_psp}{misc}{} + \entry{amd_chipsets}{misc}{} + \name{author}{1}{}{% + {{hash=ec549314e642f60d59af16514cec0835}{% + family={{Advanced Micro Devices (AMD)}}, + familyi={A\bibinitperiod}}}% + } + \strng{namehash}{ec549314e642f60d59af16514cec0835} + \strng{fullhash}{ec549314e642f60d59af16514cec0835} + \strng{bibnamehash}{ec549314e642f60d59af16514cec0835} + \strng{authorbibnamehash}{ec549314e642f60d59af16514cec0835} + \strng{authornamehash}{ec549314e642f60d59af16514cec0835} + \strng{authorfullhash}{ec549314e642f60d59af16514cec0835} + \field{extraname}{1} + \field{sortinit}{A} + \field{sortinithash}{2f401846e2029bad6b3ecc16d50031e2} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{note}{Accessed: 2024-08-17} + \field{title}{AMD Embedded Chipsets: SR5690 and SP5100} + \verb{urlraw} + \verb https://www.amd.com/en/products/embedded-chipsets + \endverb + \verb{url} + \verb https://www.amd.com/en/products/embedded-chipsets + \endverb + \endentry + \entry{amd_bsp}{manual}{} + \name{author}{1}{}{% + {{hash=ec549314e642f60d59af16514cec0835}{% + family={{Advanced Micro Devices (AMD)}}, + familyi={A\bibinitperiod}}}% + } + \strng{namehash}{ec549314e642f60d59af16514cec0835} + \strng{fullhash}{ec549314e642f60d59af16514cec0835} + \strng{bibnamehash}{ec549314e642f60d59af16514cec0835} + \strng{authorbibnamehash}{ec549314e642f60d59af16514cec0835} + \strng{authornamehash}{ec549314e642f60d59af16514cec0835} + \strng{authorfullhash}{ec549314e642f60d59af16514cec0835} + \field{extraname}{2} + \field{sortinit}{A} + \field{sortinithash}{2f401846e2029bad6b3ecc16d50031e2} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{note}{Accessed: 2024-08-17} + \field{title}{AMD Family 15h Models 30h-3Fh Processors BIOS and Kernel Developer's Guide} + \field{year}{2014} + \verb{urlraw} + \verb https://www.amd.com/system/files/TechDocs/48751_15h_Mod_30h-3Fh_BKDG.pdf + \endverb + \verb{url} + \verb https://www.amd.com/system/files/TechDocs/48751_15h_Mod_30h-3Fh_BKDG.pdf + \endverb + \endentry + \entry{altera2008}{inproceedings}{} + \name{author}{1}{}{% + {{hash=3eb79c14c66a46e93a0deec7cb61c135}{% + family={Altera®}, + familyi={A\bibinitperiod}}}% + } + \strng{namehash}{3eb79c14c66a46e93a0deec7cb61c135} + \strng{fullhash}{3eb79c14c66a46e93a0deec7cb61c135} + \strng{bibnamehash}{3eb79c14c66a46e93a0deec7cb61c135} + \strng{authorbibnamehash}{3eb79c14c66a46e93a0deec7cb61c135} + \strng{authornamehash}{3eb79c14c66a46e93a0deec7cb61c135} + \strng{authorfullhash}{3eb79c14c66a46e93a0deec7cb61c135} + \field{sortinit}{A} + \field{sortinithash}{2f401846e2029bad6b3ecc16d50031e2} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{number}{AN-520-1.0} + \field{title}{DDR3 SDRAM Memory Interface Termination and Layout Guidelines} + \field{year}{2008} + \true{nocite} + \endentry + \entry{amd_ddr3_guide}{manual}{} \name{author}{1}{}{% {{hash=48af4341f745163f945fa838eeabb062}{% family={{AMD}}, @@ -84,6 +158,60 @@ \field{sortinithash}{2f401846e2029bad6b3ecc16d50031e2} \field{labelnamesource}{author} \field{labeltitlesource}{title} + \field{note}{Available at AMD Developer Central} + \field{title}{AMD DDR3 Memory Controller: Technical Overview} + \field{year}{2011} + \verb{urlraw} + \verb https://developer.amd.com/ + \endverb + \verb{url} + \verb https://developer.amd.com/ + \endverb + \endentry + \entry{amd_6200}{manual}{} + \name{author}{1}{}{% + {{hash=48af4341f745163f945fa838eeabb062}{% + family={{AMD}}, + familyi={A\bibinitperiod}}}% + } + \strng{namehash}{48af4341f745163f945fa838eeabb062} + \strng{fullhash}{48af4341f745163f945fa838eeabb062} + \strng{bibnamehash}{48af4341f745163f945fa838eeabb062} + \strng{authorbibnamehash}{48af4341f745163f945fa838eeabb062} + \strng{authornamehash}{48af4341f745163f945fa838eeabb062} + \strng{authorfullhash}{48af4341f745163f945fa838eeabb062} + \field{extraname}{2} + \field{sortinit}{A} + \field{sortinithash}{2f401846e2029bad6b3ecc16d50031e2} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{note}{Available at AMD Developer Central} + \field{title}{AMD Opteron 6200 Series Processor} + \field{year}{2011} + \verb{urlraw} + \verb https://developer.amd.com/ + \endverb + \verb{url} + \verb https://developer.amd.com/ + \endverb + \endentry + \entry{amd_psp}{misc}{} + \name{author}{1}{}{% + {{hash=48af4341f745163f945fa838eeabb062}{% + family={{AMD}}, + familyi={A\bibinitperiod}}}% + } + \strng{namehash}{48af4341f745163f945fa838eeabb062} + \strng{fullhash}{48af4341f745163f945fa838eeabb062} + \strng{bibnamehash}{48af4341f745163f945fa838eeabb062} + \strng{authorbibnamehash}{48af4341f745163f945fa838eeabb062} + \strng{authornamehash}{48af4341f745163f945fa838eeabb062} + \strng{authorfullhash}{48af4341f745163f945fa838eeabb062} + \field{extraname}{3} + \field{sortinit}{A} + \field{sortinithash}{2f401846e2029bad6b3ecc16d50031e2} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} \field{howpublished}{\url{https://www.amd.com/en/technologies/security}} \field{note}{Accessed: 2024-07-05} \field{title}{AMD Platform Security Processor (PSP)} @@ -101,7 +229,7 @@ \strng{authorbibnamehash}{48af4341f745163f945fa838eeabb062} \strng{authornamehash}{48af4341f745163f945fa838eeabb062} \strng{authorfullhash}{48af4341f745163f945fa838eeabb062} - \field{extraname}{2} + \field{extraname}{4} \field{sortinit}{A} \field{sortinithash}{2f401846e2029bad6b3ecc16d50031e2} \field{labelnamesource}{author} @@ -110,7 +238,34 @@ \field{number}{42301} \field{title}{BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors Rev 3.14} \field{year}{2013} + \endentry + \entry{amd_ht_guide}{manual}{} + \name{author}{1}{}{% + {{hash=48af4341f745163f945fa838eeabb062}{% + family={{AMD}}, + familyi={A\bibinitperiod}}}% + } + \strng{namehash}{48af4341f745163f945fa838eeabb062} + \strng{fullhash}{48af4341f745163f945fa838eeabb062} + \strng{bibnamehash}{48af4341f745163f945fa838eeabb062} + \strng{authorbibnamehash}{48af4341f745163f945fa838eeabb062} + \strng{authornamehash}{48af4341f745163f945fa838eeabb062} + \strng{authorfullhash}{48af4341f745163f945fa838eeabb062} + \field{extraname}{5} + \field{sortinit}{A} + \field{sortinithash}{2f401846e2029bad6b3ecc16d50031e2} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{note}{Available at AMD Developer Central} + \field{title}{HyperTransport Technology: Technical Overview} + \field{year}{2011} \true{nocite} + \verb{urlraw} + \verb https://developer.amd.com/ + \endverb + \verb{url} + \verb https://developer.amd.com/ + \endverb \endentry \entry{SR5690BDG}{inbook}{} \name{author}{1}{}{% @@ -124,7 +279,7 @@ \strng{authorbibnamehash}{48af4341f745163f945fa838eeabb062} \strng{authornamehash}{48af4341f745163f945fa838eeabb062} \strng{authorfullhash}{48af4341f745163f945fa838eeabb062} - \field{extraname}{3} + \field{extraname}{6} \field{sortinit}{A} \field{sortinithash}{2f401846e2029bad6b3ecc16d50031e2} \field{labelnamesource}{author} @@ -133,7 +288,6 @@ \field{number}{43870} \field{title}{SR5690/5670/5650 BIOS Developer’s Guide 3.00} \field{year}{2010} - \true{nocite} \endentry \entry{SR5690RPR}{inbook}{} \name{author}{1}{}{% @@ -147,7 +301,7 @@ \strng{authorbibnamehash}{48af4341f745163f945fa838eeabb062} \strng{authornamehash}{48af4341f745163f945fa838eeabb062} \strng{authorfullhash}{48af4341f745163f945fa838eeabb062} - \field{extraname}{4} + \field{extraname}{7} \field{sortinit}{A} \field{sortinithash}{2f401846e2029bad6b3ecc16d50031e2} \field{labelnamesource}{author} @@ -201,9 +355,8 @@ \field{howpublished}{\url{https://www.ibm.com/history/personal-computer}} \field{title}{IBM Personal Computer} \field{year}{2024} - \true{nocite} \endentry - \entry{asus_kgpe_d16_manual}{misc}{} + \entry{asus_kgpe_d16_manual}{manual}{} \name{author}{1}{}{% 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\strng{fullhash}{0504a7a243df533003b0e6f52f3a4cbb} + \strng{bibnamehash}{2d65161a114de8ffb4c4c9e2d42eb7e2} + \strng{authorbibnamehash}{2d65161a114de8ffb4c4c9e2d42eb7e2} + \strng{authornamehash}{2d65161a114de8ffb4c4c9e2d42eb7e2} + \strng{authorfullhash}{0504a7a243df533003b0e6f52f3a4cbb} + \field{sortinit}{B} + \field{sortinithash}{d7095fff47cda75ca2589920aae98399} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{booktitle}{14th Conference of Open Innovation Association FRUCT} + \field{isbn}{1479949779} + \field{issn}{2305-7254} + \field{number}{14} + \field{title}{Too young to be secure: Analysis of UEFI threats and vulnerabilities} + \field{volume}{232} + \field{year}{2013} + \true{nocite} + \field{pages}{16\bibrangedash 24} + \range{pages}{9} + \keyw{Hardware ; Microprogramming} + \endentry + \entry{brown2003linuxbios}{inproceedings}{} + \true{moreauthor} + \true{morelabelname} + \name{author}{1}{}{% + {{hash=6d5fbc7b030fdbbd1911745166f16173}{% + family={Brown}, + familyi={B\bibinitperiod}, + given={R.\bibnamedelimi E.}, + giveni={R\bibinitperiod\bibinitdelim E\bibinitperiod}}}% + } + \strng{namehash}{04c51642671734d12e40a8fa99413da3} + \strng{fullhash}{04c51642671734d12e40a8fa99413da3} + \strng{bibnamehash}{04c51642671734d12e40a8fa99413da3} + \strng{authorbibnamehash}{04c51642671734d12e40a8fa99413da3} + \strng{authornamehash}{04c51642671734d12e40a8fa99413da3} + \strng{authorfullhash}{04c51642671734d12e40a8fa99413da3} + \field{sortinit}{B} + \field{sortinithash}{d7095fff47cda75ca2589920aae98399} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{booktitle}{Proceedings of the 2003 Linux Symposium} + \field{title}{LinuxBIOS as an Open-Source Firmware Alternative} + \field{year}{2003} + \endentry \entry{chang2013}{article}{} \name{author}{2}{}{% {{hash=701500fa4f83c75c8ce39152916ce4e4}{% @@ -258,6 +486,196 @@ \verb 10.1007/s10207-013-0191-1 \endverb \endentry + \entry{ChengKaixing2021TOWo}{article}{} + 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Conference series} + \field{number}{4} + \field{title}{Attacking Intel UEFI by Using Cache Poisoning} + \field{volume}{1187} + \field{year}{2019} + \true{nocite} + \field{pages}{42072\bibrangedash} + \range{pages}{-1} + \keyw{Alliances ; Integrated circuits ; Poisoning} + \endentry + \entry{WaqarMuhammad2021DDCF}{article}{} + \name{author}{4}{}{% + {{hash=ee5704d66d59e3cff0ccd7340680b3cb}{% + family={Waqar}, + familyi={W\bibinitperiod}, + given={Muhammad}, + giveni={M\bibinitperiod}}}% + {{hash=394c7290cf8ce4e9e957f8b00086ad41}{% + family={Bak}, + familyi={B\bibinitperiod}, + given={Geunyong}, + giveni={G\bibinitperiod}}}% + {{hash=1f079894ae531411ed1de72354831c91}{% + family={Kwon}, + familyi={K\bibinitperiod}, + given={Junhyeong}, + giveni={J\bibinitperiod}}}% + {{hash=5b2467e0abbadb6813f15043a1171386}{% + family={Baeg}, + familyi={B\bibinitperiod}, + given={Sanghyeon}, + giveni={S\bibinitperiod}}}% + } + \list{language}{1}{% + {eng}% + } + \list{location}{1}{% + {Piscataway}% + } + \list{publisher}{1}{% + {IEEE}% + } + \strng{namehash}{0bdeb802bff85655b14b4864aea757ce} + \strng{fullhash}{eaa8d50f0a408c25fab46e0a4aafbb9f} + \strng{bibnamehash}{0bdeb802bff85655b14b4864aea757ce} + \strng{authorbibnamehash}{0bdeb802bff85655b14b4864aea757ce} + \strng{authornamehash}{0bdeb802bff85655b14b4864aea757ce} + \strng{authorfullhash}{eaa8d50f0a408c25fab46e0a4aafbb9f} + \field{sortinit}{W} + \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{issn}{2169-3536} + \field{journaltitle}{IEEE access} + \field{title}{DDR4 Data Channel Failure Due to DC Offset Caused by Intermittent Solder Ball Fracture in FBGA Package} + \field{volume}{9} + \field{year}{2021} + \true{nocite} + \field{pages}{63002\bibrangedash 63011} + \range{pages}{10} + \keyw{Capacitors ; Couplings ; Printed circuits} + \endentry \entry{AGESA_wiki}{misc}{} \name{author}{1}{}{% {{hash=b6aea1a416c89509a7df1cbb69249cb6}{% @@ -1046,7 +2502,7 @@ \verb https://en.wikipedia.org/w/index.php?title=AMD_Platform_Security_Processor&oldid=1216563013 \endverb \endentry - \entry{DDR3_wiki}{misc}{} + \entry{wiki_bios}{misc}{} \name{author}{1}{}{% {{hash=b6aea1a416c89509a7df1cbb69249cb6}{% family={{Wikipedia contributors}}, @@ -1063,6 +2519,28 @@ \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} \field{labeltitlesource}{title} + \field{howpublished}{\url{https://en.wikipedia.org/w/index.php?title=BIOS&oldid=1240397019}} + \field{note}{[Online; accessed 16-August-2024]} + \field{title}{BIOS --- {Wikipedia}{,} The Free Encyclopedia} + \field{year}{2024} + \endentry + \entry{DDR3_wiki}{misc}{} + \name{author}{1}{}{% + {{hash=b6aea1a416c89509a7df1cbb69249cb6}{% + family={{Wikipedia contributors}}, + familyi={W\bibinitperiod}}}% + } + \strng{namehash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{fullhash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{bibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} + \field{extraname}{4} + \field{sortinit}{W} + \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} \field{note}{[Online; accessed 8-May-2024]} \field{title}{DDR3 SDRAM --- {Wikipedia}{,} The Free Encyclopedia} \field{year}{2024} @@ -1086,7 +2564,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{4} + \field{extraname}{5} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1114,7 +2592,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{5} + \field{extraname}{6} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1142,7 +2620,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{6} + \field{extraname}{7} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1170,7 +2648,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{7} + \field{extraname}{8} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1198,7 +2676,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{8} + \field{extraname}{9} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1226,7 +2704,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{9} + \field{extraname}{10} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1254,7 +2732,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{10} + \field{extraname}{11} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1282,7 +2760,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{11} + \field{extraname}{12} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1310,7 +2788,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{12} + \field{extraname}{13} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1338,7 +2816,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{13} + \field{extraname}{14} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1354,6 +2832,28 @@ \verb https://en.wikipedia.org/w/index.php?title=Non-disclosure_agreement&oldid=1183749255 \endverb \endentry + \entry{northbridge_wiki}{misc}{} + \name{author}{1}{}{% + {{hash=b6aea1a416c89509a7df1cbb69249cb6}{% + family={{Wikipedia contributors}}, + familyi={W\bibinitperiod}}}% + } + \strng{namehash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{fullhash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{bibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} + \field{extraname}{15} + \field{sortinit}{W} + \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{howpublished}{\url{https://en.wikipedia.org/w/index.php?title=Northbridge_(computing)&oldid=1231509957}} + \field{note}{[Online; accessed 17-August-2024]} + \field{title}{Northbridge (computing) --- {Wikipedia}{,} The Free Encyclopedia} + \field{year}{2024} + \endentry \entry{openbmc_wiki}{misc}{} \name{author}{1}{}{% {{hash=b6aea1a416c89509a7df1cbb69249cb6}{% @@ -1366,7 +2866,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{14} + \field{extraname}{16} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1394,7 +2894,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{15} + \field{extraname}{17} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1410,6 +2910,28 @@ \verb https://en.wikipedia.org/w/index.php?title=SeaBIOS&oldid=1179465237 \endverb \endentry + \entry{southbridge_wiki}{misc}{} + \name{author}{1}{}{% + {{hash=b6aea1a416c89509a7df1cbb69249cb6}{% + family={{Wikipedia contributors}}, + familyi={W\bibinitperiod}}}% + } + \strng{namehash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{fullhash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{bibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} + \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} + \field{extraname}{18} + \field{sortinit}{W} + \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{howpublished}{\url{https://en.wikipedia.org/w/index.php?title=Southbridge_(computing)&oldid=1239483618}} + \field{note}{[Online; accessed 17-August-2024]} + \field{title}{Southbridge (computing) --- {Wikipedia}{,} The Free Encyclopedia} + \field{year}{2024} + \endentry \entry{4freedom_wiki}{misc}{} \name{author}{1}{}{% {{hash=b6aea1a416c89509a7df1cbb69249cb6}{% @@ -1422,7 +2944,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{16} + \field{extraname}{19} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1450,7 +2972,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{17} + \field{extraname}{20} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1478,7 +3000,7 @@ \strng{authorbibnamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authornamehash}{b6aea1a416c89509a7df1cbb69249cb6} \strng{authorfullhash}{b6aea1a416c89509a7df1cbb69249cb6} - \field{extraname}{18} + \field{extraname}{21} \field{sortinit}{W} \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} \field{labelnamesource}{author} @@ -1494,6 +3016,31 @@ \verb https://en.wikipedia.org/w/index.php?title=X86&oldid=1221800539 \endverb \endentry + \entry{winbond}{manual}{} + \name{author}{1}{}{% + {{hash=506790477fe03844712a0c66579f17d0}{% + family={{Winbond Electronics Corporation}}, + familyi={W\bibinitperiod}}}% + } + \strng{namehash}{506790477fe03844712a0c66579f17d0} + \strng{fullhash}{506790477fe03844712a0c66579f17d0} + \strng{bibnamehash}{506790477fe03844712a0c66579f17d0} + \strng{authorbibnamehash}{506790477fe03844712a0c66579f17d0} + \strng{authornamehash}{506790477fe03844712a0c66579f17d0} + \strng{authorfullhash}{506790477fe03844712a0c66579f17d0} + \field{sortinit}{W} + \field{sortinithash}{4315d78024d0cea9b57a0c6f0e35ed0d} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{note}{Accessed: 2024-08-17} + \field{title}{WINBOND W83667HG-A Datasheet} + \verb{urlraw} + \verb https://www.winbond.com/ + \endverb + \verb{url} + \verb https://www.winbond.com/ + \endverb + \endentry \entry{wolf2006}{article}{} \name{author}{1}{}{% {{hash=e7ea35f3f0c3cf77495520fc0d8fdb22}{% @@ -1523,6 +3070,54 @@ \verb 10.1109/MC.2006.156 \endverb \endentry + \entry{YiJinhui2021DoDS}{article}{} + \name{author}{3}{}{% + {{hash=a738e2c330fa8bb553322676f86cdd67}{% + family={Yi}, + familyi={Y\bibinitperiod}, + given={Jinhui}, + giveni={J\bibinitperiod}}}% + {{hash=1ec6f5d17a25af4f2091741966c18325}{% + family={Wang}, + familyi={W\bibinitperiod}, + given={Mingfu}, + giveni={M\bibinitperiod}}}% + {{hash=90c8def289747c02c6ba0fa10c44c4d4}{% + family={Bai}, + familyi={B\bibinitperiod}, + given={Lidong}, + giveni={L\bibinitperiod}}}% + } + \list{language}{1}{% + {eng}% + } + \list{location}{1}{% + {Bristol}% + } + \list{publisher}{1}{% + {IOP Publishing}% + } + \strng{namehash}{f0fa6bd8023def40891dba2f4d00ecb2} + \strng{fullhash}{f0fa6bd8023def40891dba2f4d00ecb2} + \strng{bibnamehash}{f0fa6bd8023def40891dba2f4d00ecb2} + \strng{authorbibnamehash}{f0fa6bd8023def40891dba2f4d00ecb2} + \strng{authornamehash}{f0fa6bd8023def40891dba2f4d00ecb2} + \strng{authorfullhash}{f0fa6bd8023def40891dba2f4d00ecb2} + \field{sortinit}{Y} + \field{sortinithash}{fd67ad5a9ef0f7456bdd9aab10fe1495} + \field{labelnamesource}{author} + \field{labeltitlesource}{title} + \field{issn}{1742-6588} + \field{journaltitle}{Journal of physics. Conference series} + \field{number}{1} + \field{title}{Design of DDR3 SDRAM read-write controller based on FPGA} + \field{volume}{1846} + \field{year}{2021} + \true{nocite} + \field{pages}{12046\bibrangedash} + \range{pages}{-1} + \keyw{Cameras ; Optical fibers ; Physics ; Realtime . . .} + \endentry \enddatalist \endrefsection \endinput diff --git a/hardware_init_review.pdf b/hardware_init_review.pdf index 95b1dac..6cfe960 100644 Binary files a/hardware_init_review.pdf and b/hardware_init_review.pdf differ diff --git a/hardware_init_review.tex b/hardware_init_review.tex index 11ddb34..1d28c39 100644 --- a/hardware_init_review.tex +++ b/hardware_init_review.tex @@ -48,7 +48,9 @@ Free Documentation License". The global trend is towards the scarcity of free software-compatible hardware, and soon there will be no computer that will work without software domination -by big companies, especially involving BIOSes. A Basic Input Output System +by big companies, especially involving firmware like BIOSes. \\ + +A Basic Input Output System (BIOS) was originally a set of low-level functions contained in the read-only memory of a computer's mainboard, enabling it to perform basic operations when powered up. However, the definition of a BIOS has evolved to include what used @@ -61,50 +63,67 @@ performance, making the code complex, as its role is to optimize several parallel buses operating at high speeds and shared by many CPU cores, and make them act as a homogeneous whole. \\ -This documentation is the product of a project hosted by the \textit{LIP6 laboratory} and supported by the \textit{GNU Boot Project} and the \textit{Free Software Foundation}, delves into the importance of firmware in the hardware initialization of modern computers. -It explores various aspects of firmware, such as Intel Management -Engine (ME), AMD Platform Security Processor (PSP), Advanced Configuration and -Power Interface (ACPI), and System Management Mode (SMM). Additionally, it -provides an in-depth look at memory initialization and training algorithms, -highlighting their critical role in system stability and performance. \\ - -Examples of the implementation in the Asus KGPE-D16 mainboard are presented, describing its hardware characteristics, topology, and the crucial role of firmware in its operation after the mainboard architecture is examined. +This document is the product of a project hosted by the \textit{LIP6 laboratory} +and supported by the \textit{GNU Boot Project} and the \textit{Free Software +Foundation}. It delves into the importance of firmware in the hardware +initialization of modern computers and explores various aspects of firmware, +such as Intel Management Engine (ME), AMD Platform Security Processor (PSP), +Advanced Configuration and Power Interface (ACPI), and System Management Mode +(SMM). Additionally, it provides an in-depth look at memory initialization and +training algorithms, highlighting their critical role in system stability +and performance. Examples of the implementation in the ASUS KGPE-D16 mainboard are +presented, describing its hardware characteristics, topology, and the crucial role +of firmware in its operation after the mainboard architecture is examined. Practical examples illustrate the impact of firmware on hardware initialization, memory optimization, resource allocation, power management, and security. Specific algorithms used for memory training and their outcomes are analyzed to demonstrate the complexity and importance of firmware in -achieving optimal system performance. \\ - -Furthermore, the article explores the relationship between firmware and +achieving optimal system performance. +Furthermore, this document explores the relationship between firmware and hardware virtualization, discussing how modern firmware supports and enhances virtualized environments. Security considerations and future trends in firmware development are also addressed, emphasizing the need for continued -research and advocacy for free software-compatible hardware. The article -concludes with a call to action, urging the development of libre -firmware solutions to ensure greater control and security in computing. +research and advocacy for free software-compatible hardware. \chapter{Introduction to firmware and BIOS evolution} \section{Historical context of BIOS} - + \subsection{Definition and origin} + + The BIOS (Basic Input/Output System) is firmware, which is a type of software + that is embedded into hardware devices to control their basic functions, + acting as a bridge between hardware and other software, ensuring that the + hardware operates correctly. Unlike regular software, firmware is usually + stored in a non-volatile memory like ROM or flash memory. The term "firmware" + comes from its role: it is "firm" because it's more permanent than regular + software (which can be easily changed) but not as rigid as hardware. \\ - The BIOS (Basic Input/Output System) is firmware used to perform hardware - initialization during the booting process and to provide runtime services - for operating systems and programs. Being a critical component for the - startup of personal computers, acting as an intermediary between the - computer's hardware and its operating system, the BIOS is embedded on a - chip on the motherboard and is the first code that runs when a PC is - powered on. The concept of BIOS has its roots in the early days of personal + The BIOS is used to perform initialization during the booting process + and to provide runtime services for operating systems and programs. + Being a critical component for the startup of personal computers, + acting as an intermediary between the computer's hardware and its + operating system, the BIOS is embedded on a chip on the motherboard and + is the first code that runs when a PC is powered on. + The concept of BIOS has its roots in the early days of personal computing. It was first developed by IBM for their IBM PC, which was - introduced in 1981. The term BIOS itself was coined by Gary Kildall, who - developed the CP/M (Control Program for Microcomputers) operating system. - In CP/M, BIOS was used to describe a component that interfaced directly - with the hardware, allowing the operating system to be somewhat - hardware-independent. \newline + introduced in 1981 \cite{freiberger2000fire}. + The term BIOS itself was coined by Gary Kildall, who developed the CP/M + (Control Program for Microcomputers) operating + system \cite{shustek2016kildall}. In CP/M, BIOS was used to describe a + component that interfaced directly with the hardware, allowing the operating + system to be somewhat hardware-independent. \newline + + \begin{figure}[H] + \centering + \includegraphics[width=0.5\textwidth]{images/IBM_logo.png} + \caption{The eight-striped wordmark of IBM (1967, public domain, + trademarked)} + \end{figure} IBM's implementation of BIOS became a de facto standard in the industry, - as it was part of the IBM PC's open architecture, which refers to the + as it was part of the IBM PC's open + architecture \cite{grewal_ibm_pc}\cite{ibm_pc}, which refers to the design philosophy adopted by IBM when developing the IBM Personal Computer (PC), introduced in 1981. This architecture is characterized by the use of off-the-shelf components and publicly available specifications, which @@ -123,22 +142,18 @@ firmware solutions to ensure greater control and security in computing. same in principle. IBM also published detailed technical documentation at that time, including circuit diagrams, BIOS listings, and interface specifications. This transparency allowed other companies to understand and - replicate the IBM PC's functionality. - + replicate the IBM PC's functionality \cite{freiberger2000fire}. + \subsection{Functionalities and limitations} - - The Basic Input/Output System (BIOS) is a foundational firmware component - in early personal computers, responsible for initializing hardware and - booting the operating system. Developed as part of IBM's original PC - design, the BIOS provided essential functionalities. \newline When a computer is powered on, the BIOS executes a Power-On Self-Test (POST), a diagnostic sequence that verifies the integrity and functionality of critical hardware components such as the CPU, RAM, disk drives, - keyboard, and other peripherals. This process ensures that all essential - hardware components are operational before the system attempts to load the - operating system. If any issues are detected, the BIOS generates error - messages or beep codes to alert the user. + keyboard, and other peripherals \cite{wiki_bios}. + This process ensures that all essential hardware components are operational + before the system attempts to load the operating system. + If any issues are detected, the BIOS generates error messages or beep codes + to alert the user. Following the successful completion of POST, the BIOS runs the bootstrap loader, a small program that identifies the operating system's bootloader on a storage device, such as a hard drive, floppy disk, or optical drive. @@ -152,7 +167,14 @@ firmware solutions to ensure greater control and security in computing. accessing disk drives, without needing to manage the hardware directly. By providing standardized interfaces for hardware components, the BIOS simplifies software development and improves compatibility across different - hardware configurations. \newline + hardware configurations \cite{ibm_pc}. \newline + + \begin{figure}[H] + \centering + \includegraphics[width=0.5\textwidth]{images/bios_chip.jpg} + \caption{An AMI BIOS chip from a Dell 310, by Jud McCranie + (CC BY-SA 4.0, 2018)} + \end{figure} Despite its essential role, the early BIOS had several limitations. One significant limitation was its limited storage capacity. @@ -175,13 +197,12 @@ firmware solutions to ensure greater control and security in computing. slower compared to later direct access methods provided by operating systems, resulting in performance bottlenecks, especially for disk-intensive operations. This inflexibility restricts the ability to - support new hardware and technologies efficiently. + support new hardware and technologies efficiently\cite{anderson_2018}. Early BIOS implementations also had minimal security features. There were no mechanisms to verify the integrity of the BIOS code or to protect against unauthorized modifications, leaving systems vulnerable to attacks that could alter the BIOS and potentially compromise the entire system, - such as rootkits and firmware viruses. - + such as rootkits and firmware viruses. Added to that, the traditional BIOS operates in 16-bit real mode, a constraint that limits the amount of code and memory it can address. This limitation hinders the performance and complexity of firmware, making @@ -194,17 +215,17 @@ firmware solutions to ensure greater control and security in computing. Furthermore, the traditional BIOS has limited flexibility and is challenging to update or extend. This inflexibility restricts the ability to support new hardware and technologies efficiently - \cite{smith_2017}\cite{acmcs2015}. + \cite{anderson_2018}\cite{acmcs2015}. \section{Modern BIOS and UEFI} \subsection{Transition from traditional BIOS to UEFI (Unified Extensible Firmware Interface)} - - All the limitations listed earlier have necessitated a transition to a more + + All the limitations listed earlier caused a transition to a more modern firmware interface, designed to address the shortcomings of the traditional BIOS. This section delves into the historical context of this shift, the driving factors behind it, and the advantages UEFI offers over - the traditional BIOS. + the traditional BIOS. \\ The development of UEFI began in the mid-1990s as part of the Intel Boot Initiative, which aimed to modernize the boot process and overcome the @@ -212,7 +233,13 @@ firmware solutions to ensure greater control and security in computing. consortium of technology companies including Intel, AMD, and Microsoft, had formalized the UEFI specification \cite{uefi_spec}. UEFI was designed to address the shortcomings of the traditional BIOS, providing several key - improvements. \newline + improvements. + + \begin{figure}[H] + \centering + \includegraphics[width=0.25\textwidth]{images/uefi_logo.png} + \caption{The UEFI logo (public domain, 2010)} + \end{figure} One of the most significant advancements of UEFI is its support for 32-bit and 64-bit modes, allowing it to address more memory and run more complex @@ -222,16 +249,17 @@ firmware solutions to ensure greater control and security in computing. supporting disks larger than 2 terabytes and allowing for a nearly unlimited number of partitions \cite{microsoft_uefi}\cite{russinovich2012}. + Improved boot performance is another driving factor. UEFI provides faster boot times compared to the traditional BIOS, thanks to its efficient hardware and software initialization processes. This improvement is particularly beneficial for systems with complex hardware configurations, - where quick boot times are essential \cite{intel_uefi}. + where quick boot times are essential \cite{intel_uefi}. UEFI's modular architecture makes it more extensible and easier to update compared to the traditional BIOS. This design allows for the addition of drivers, applications, and other components without requiring a complete firmware overhaul, providing greater flexibility and adaptability to new - technologies \cite{smith_2017}\cite{acmcs2015}. UEFI also includes enhanced + technologies \cite{acmcs2015}. UEFI also includes enhanced security features such as \textit{Secure Boot}, which ensures that only trusted software can be executed during the boot process, thereby protecting the system from unauthorized modifications and malware @@ -242,31 +270,30 @@ firmware solutions to ensure greater control and security in computing. including Intel, AMD, and Microsoft, have adopted UEFI as the new standard for firmware interfaces, ensuring broad compatibility and interoperability \cite{uefi_spec}. - - \subsection{An other way with coreboot} - + + \subsection{An other way with \textit{coreboot}} + While UEFI has become the dominant firmware interface for modern computing systems, it is not without its critics. Some of the primary concerns about UEFI include its complexity, potential security vulnerabilities, and the degree of control it provides to hardware manufacturers over the boot - process. As an alternative to UEFI, coreboot offers a different approach to - firmware that aims to address some of these concerns and continue the - evolution of BIOS. - \textit{coreboot}, originally known as LinuxBIOS, is a free firmware + process. + Originally known as LinuxBIOS, \textit{coreboot}, is a free firmware project initiated in 1999 by Ron Minnich and his team at the Los Alamos National Laboratory. The project's primary goal was to create a fast, lightweight, and flexible firmware solution that could initialize hardware and boot operating systems quickly, while remaining transparent and - auditable\cite{coreboot}. \newline + auditable\cite{coreboot}. As an alternative to UEFI, \textit{coreboot} + offers a different approach to firmware that aims to address some of these + concerns and continue the evolution of BIOS.\newline One of the main advantages of \textit{coreboot} over UEFI is its - simplicity. - \textit{coreboot} is designed to perform only the minimal tasks required to + simplicity, as it is designed to perform only the minimal tasks required to initialize hardware and pass control to a payload, such as a bootloader or operating system kernel. This minimalist approach reduces the attack surface and potential for security vulnerabilities, as there is less code - that could be exploited by malicious actors \cite{rudolph2007}. + that could be exploited by malicious actors \cite{rudolph2007}. Another significant benefit of \textit{coreboot} is its libre nature. Unlike UEFI, which is controlled by a consortium of hardware and software vendors, @@ -276,146 +303,620 @@ firmware solutions to ensure greater control and security in computing. and developers can review the code for potential vulnerabilities and contribute to its improvement, fostering a community-driven approach to firmware development\cite{coreboot}. - \textit{coreboot} also supports a wide range of payloads, allowing users to + This project also supports a wide range of bootloaders, called payloads, + allowing users to customize their boot process to suit their specific needs. Popular payloads include SeaBIOS, which provides legacy BIOS compatibility, and Tianocore, which offers UEFI functionality within the \textit{coreboot} framework. - This - flexibility allows \textit{coreboot} to be used in a variety of - environments, from - embedded systems to high-performance servers\cite{coreboot_payloads}. + This flexibility allows \textit{coreboot} to be used in a variety of + environments, from embedded systems to high-performance + servers \cite{coreboot_payloads}. \newline + \begin{figure}[H] + \centering + \includegraphics[width=0.3\textwidth]{images/coreboot_logo.png} + \caption{The \textit{coreboot} logo, by Konsult Stuge \& coresystems + (coreboot logo license, 2008)} + \end{figure} + Despite its advantages, \textit{coreboot} is not without its challenges. The project relies heavily on community contributions, and support for new hardware often lags behind that of UEFI. Additionally, the minimalist design of - \textit{coreboot} means that some advanced features provided by UEFI, such - as Secure - Boot, are not available by default. However, the \textit{coreboot} - community + \textit{coreboot} means that some advanced features provided by UEFI are not + available by default. However, the \textit{coreboot} community continues to work on adding new features and improving compatibility with - modern hardware\cite{coreboot_challenges}. + modern hardware or security issues \cite{coreboot_challenges}. For example, + it provides a \textit{verified boot} function, allowing to prevent + rootkits and other attacks based on firmware modifications + \cite{coreboot_docs}. However, it's important to note that \textit{coreboot} is not entirely free - in all - aspects. Many modern processors and chipsets require proprietary binary - blobs for certain functionalities, such as memory initialization and - hardware management. These blobs are necessary for \textit{coreboot} to - function - correctly on a wide range of hardware, but they compromise the goal of - having a fully free firmware one day\cite{blobs}. + in all aspects. Many modern processors and chipsets require + \textit{proprietary blobs}, short for \textit{Binary Large Object}, which + is a collection of binary data stored as a single entity. These blobs are + necessary for \textit{coreboot} to function correctly on a wide range of + hardware, but they compromise the goal of having a fully free firmware one + day \cite{blobs}, since these blobs are used for certain functionalities such + as memory initialization and hardware management. + + \begin{figure}[H] + \centering + \includegraphics[width=0.25\textwidth]{images/gnuboot.png} + \caption{The \textit{GNU Boot} logo, by Jason Self (CC0, 2020)} + \end{figure} + To address these concerns, the GNU Project has developed GNU Boot, a fully free distribution of firmware, including \textit{coreboot}, that aims to be entirely free by avoiding the use of proprietary binary blobs. GNU Boot is committed to using only free software for all aspects of firmware, making it a preferred choice for users and organizations that prioritize software - freedom and transparency\cite{gnuboot}. + freedom and transparency \cite{gnuboot}. \section{Shift in firmware responsibilities} - Initially, we saw that the BIOS's primary function was to perform the - Power-On Self-Test (POST), a basic diagnostic testing process to check the - system's hardware components and ensure they were functioning correctly. - This included verifying the CPU, memory, and essential peripherals before - passing control to the operating system's bootloader. This process was - relatively simple, given the limited capabilities and straightforward - architecture of early computer systems\cite{smith_2017}. As computer - systems advanced, particularly with the advent of more sophisticated memory - technologies, the role of the BIOS expanded significantly. An example is - that modern memory modules operate at much higher speeds and capacities - than their predecessors, requiring precise configuration to ensure - stability and optimal performance. - We'll see in following sections how memory is taken care by firmware, - since the memory controller, a critical component in modern computer - systems, manages the data flow between the processor and memory modules. - Firmware then plays a crucial role in configuring this controller - during the boot process. This configuration includes setting memory - frequencies, voltage levels, and timing parameters to match the - specifications of the installed memory\cite{uefi_spec}. - The enhanced role of firmware in memory training and optimization directly - impacts system performance and stability. For example, overclocking - involves configuring the system to run at higher speeds than - manufacturer-specified limits. Firmware plays a key role in enabling - and managing overclocking, particularly for the memory subsystem. By - allowing adjustments to memory frequencies, voltages, and timings, it - provides tools for performance tuning while including safeguards to manage - the risks of instability and hardware damage \cite{anderson_2018}. + Initially, the BIOS's primary function was to perform the POST, a basic + diagnostic testing process to check the system's hardware + components and ensure they were functioning correctly. This included verifying + the CPU, memory, and essential peripherals before passing control to the + operating system's bootloader. This process was relatively simple, given the + limited capabilities and straightforward architecture of early computer + systems \cite{anderson_2018}. -\chapter{Characteristics of Asus KGPE-D16 Mainboard} + As computer systems advanced, particularly with the advent of more + sophisticated memory technologies, the role of firmware expanded + significantly. Modern memory modules operate at much higher speeds and + capacities than their predecessors, requiring precise configuration to ensure + stability and optimal performance. Firmware now plays a critical role in + managing the memory controller, which is responsible for regulating data flow + between the processor and memory modules. This includes configuring memory + frequencies, voltage levels, and timing parameters to match the specifications + of the installed memory \cite{uefi_spec}\cite{BKDG}. + Beyond memory management, firmware responsibilities have broadened to + encompass a wide range of system-critical tasks. One key area is power + management, where firmware is responsible for optimizing energy consumption + across various components of the system. Efficient power management is + essential not only for extending battery life in portable devices + but also for reducing thermal output and ensuring system longevity in desktop + and server environments. + Moreover, modern firmware takes on significant roles in hardware + initialization and configuration, which were traditionally handled by the + operating system. For example, the initialization of USB controllers, network + interfaces, and storage devices is now often managed by the firmware during + the early stages of the boot process. This shift ensures that the operating + system can seamlessly interact with hardware from the moment it takes control, + reducing boot times and improving overall system + reliability \cite{uefi_spec}. + Security has also become a paramount concern for modern firmware. UEFI + (Unified Extensible Firmware Interface), which has largely replaced + traditional BIOS in modern systems, includes features which + prevents unauthorized or malicious software from loading during the boot + process. This helps protect the system from rootkits and other low-level + malware that could compromise the integrity of the operating system before it + even starts \cite{uefi_spec}. + In the context of performance tuning, firmware sometimes also plays a key + role in enabling and managing overclocking, particularly for the memory + subsystem. By allowing adjustments to memory frequencies, voltages, and + timings, firmware provides tools for enthusiasts to push their systems beyond + default limits. At the same time, it includes safeguards to + manage the risks of instability and hardware damage, balancing performance + gains with system reliability \cite{anderson_2018}. \\ - \section{Overview of Asus KGPE-D16 Hardware} - \begin{itemize} - \item Description of the mainboard's hardware components - \begin{itemize} - \item CPU: Support for AMD Opteron 6000 series processors - \item RAM: 16 DDR3 DIMM slots supporting up to 256GB of memory - \item Expansion Slots: Multiple PCIe slots for expandability - \item Storage: SATA ports and potential for RAID configurations - \item Networking: Integrated dual gigabit Ethernet ports - \item Other Peripherals: USB ports, audio outputs, and additional I/O ports - \end{itemize} - \item Topology and Layout - \begin{itemize} - \item Physical layout of the mainboard - \item Placement of key components and their interactions - \item Cooling and power distribution - \end{itemize} - \end{itemize} + In summary, the evolution of firmware from simple hardware initialization + routines to complex management systems reflects the increasing sophistication + of modern computer architectures. Firmware is now a critical layer that not + only ensures the correct functioning of hardware components but also optimizes + performance, manages power consumption, and enhances system security, making + it an indispensable part of contemporary computing. \\ - \section{Firmware's Role in Asus KGPE-D16} - \begin{itemize} - \item Initial hardware setup - \item Memory training and optimization - \item Resource allocation and conflict resolution - \item Power management and efficiency - \item Security features and updates - \end{itemize} + This document will focus on \textit{coreboot} during the next parts + to study how modern firmware interact with hardware and also as a basis for + improvements. -\chapter{Key Components in Modern Firmware} +\chapter{Characteristics of ASUS KGPE-D16 mainboard} - \section{Advanced Configuration and Power Interface (ACPI)} - \begin{itemize} - \item Detailed explanation of ACPI - \item Role in power management and system configuration - \item Implementation in modern operating systems - \item \textbf{Asus KGPE-D16 Example}: ACPI utilization in power management and device configuration on the mainboard - \end{itemize} + \begin{figure}[H] + \centering + \includegraphics[width=0.9\textwidth]{images/kgpe-d16.png} + \caption{The KGPE-D16 (CC BY-SA 4.0, 2021)} + \end{figure} + + \newpage - \section{System Management Mode (SMM)} - \begin{itemize} - \item Definition and significance - \item How SMM enhances system security - \item Examples of SMM applications in real-world systems - \item \textbf{Asus KGPE-D16 Example}: SMM features and their impact on system security and functionality in the KGPE-D16 - \end{itemize} + \section{Overview of ASUS KGPE-D16 hardware} - \section{AMD Platform Security Processor (PSP) and Intel Management Engine (ME)} - \begin{itemize} - \item Overview and purpose - \item Security implications, concerns and controversies - \item Interaction with system firmware - \item Differences between Intel ME and AMD PSP - \end{itemize} + The ASUS KGPE-D16 server mainboard is a dual-socket motherboard designed to + support AMD Family 10h/15h series processors. Released in 2009, this mainboard + was later awarded the \textit{Respects Your Freedom} (RYF) certification in + March 2017, underscoring its commitment to fully free software compatibility + \cite{fsf_ryf}. \\ -\chapter{Memory Initialization and Training Algorithms} + This mainboard is equipped with robust hardware components designed to meet the + demands of high-performance computing. It features 16 DDR3 DIMM + slots, capable of supporting up to 256GB of memory, although certain + configurations may be limited to 192GB, with some reports suggesting the + potential to support 256GB under specific conditions. + In terms of expandability, the KGPE-D16 includes multiple PCIe slots, with five + physical slots available, although only four can be used simultaneously due to + slot sharing. For storage, the mainboard provides + several SATA ports. Networking capabilities are enhanced by integrated dual + gigabit Ethernet ports, which provide high-speed connectivity essential for + data-intensive tasks and network communication \cite{ASUS_kgpe_d16_manual}. + Additionally, the board is equipped with various peripheral interfaces, + including USB ports, audio outputs, and other I/O ports, ensuring compatibility + with a wide range of external devices. - \section{Importance of Memory Initialization} + \begin{figure}[H] + \centering + \includegraphics[width=0.8\textwidth]{images/fig1_schema_basique.png} + \caption{Basic schematics of the ASUS KGPE-D16 Mainboard, ASUS (2011)} + \label{fig:d16_basic_schematics} + \end{figure} + + The physical layout of the ASUS KGPE-D16 is meticulously designed to optimize + airflow, cooling, and power distribution. All of this is critical for + maintaining system stability, particularly under heavy computational loads, as + this board was designed for server operations. In particular, key components + such as the CPU sockets, memory slots, and PCIe slots are strategically + positioned. \\ + + \begin{figure}[H] + \centering + \includegraphics[width=0.8\textwidth]{images/kgpe-d16_real.png} + \caption{The KGPE-D16, viewed from the top (CC BY-SA 4.0, 2024)} + \label{fig:d16_top_view} + \end{figure} + + \section{Chipset} + + Before diving into the specific components, it is essential to understand the + roles of the northbridge and southbridge in traditional motherboard + architecture. These chipsets historically managed communication between the CPU + and other critical components of the system \cite{amd_chipsets}. \\ + + The northbridge is a chipset on the motherboard that traditionally manages + high-speed communication between the CPU, memory (RAM), and graphics card (if + applicable). It serves as a hub for data that needs to move quickly between + these components. On the ASUS KGPE-D16, the functions typically associated with + the northbridge are divided between the CPU’s internal northbridge and an + external SR5690 northbridge chip. The SR5690 specifically acts as a translator + and switch, handling the HyperTransport interface, a high-speed communication + protocol used by AMD processors, and converting it to ALink and PCIe interfaces, + which are crucial for connecting + peripherals like graphics cards \cite{SR5690BDG}. + Additionally, + the northbridge on the KGPE-D16 incorporates the IOMMU (Input-Output Memory + Management Unit), which is crucial for ensuring secure and efficient memory + access by I/O devices. The IOMMU allows for the virtualization of memory + addresses, providing device isolation and preventing unauthorized memory access, + which is particularly important in environments that run multiple virtual + machines \cite{amd_chipsets}\cite{northbridge_wiki}. \\ + + The southbridge, on the other hand, is responsible for handling lower-speed, + peripheral interfaces such as the PCI, USB, and IDE/SATA connections, as well as + managing onboard audio and network controllers. On the KGPE-D16, these functions + are managed by the SP5100 southbridge chip, which integrates several critical + functions including the LPC bridge, SATA controllers, and other essential I/O + operations \cite{amd_chipsets}\cite{southbridge_wiki}. + It is essentially an ALink bus controller and includes the hardware interrupt + controller, the IOAPIC. Interrupts from peripheral always pass + through the northbridge (fig. \ref{fig:d16_ioapic}), since it translates ALink + to HyperTransport for the CPUs and contains the IOMMU \cite{SR5690BDG}. \\ + + \begin{figure}[H] + \centering + \includegraphics[width=0.9\textwidth]{images/ioapic.png} + \caption{Functional diagram presenting the IOAPIC function of the SP5100, + ASUS (2011)} + \label{fig:d16_ioapic} + \end{figure} + + In addition to the northbridge and southbridge, the KGPE-D16 also contains + specialized chips for managing input/output operations and system health + monitoring. The WINBOND W83667HG-A Super I/O chip handles traditional I/O + functions such as legacy serial and parallel ports, keyboard, and mouse + interfaces, but also the SPI chip that contains the firmware + \cite{winbond}. Meanwhile, the Nuvoton W83795G/ADG Hardware Monitor + oversees the system’s health by monitoring temperatures, voltages, and fan + speeds, ensuring that the system operates within safe parameters \cite{nuvoton}. + On the KGPE-D16, access to the Super I/O from a CPU core is done through the + SR5690, then the SP5100, as that can be observed on the functional diagram of + the chipset (fig. \ref{fig:d16_chipset}) \cite{SR5690BDG}. + + \begin{figure}[H] + \centering + \includegraphics[width=0.8\textwidth]{images/fig2_diagramme_chipset.png} + \caption{Functional diagram of the KGPE-D16 chipset (CC BY-SA 4.0, 2024)} + \label{fig:d16_chipset} + \end{figure} + + \section{Processors} + + The ASUS KGPE-D16 supports AMD Family 10h processors, but it is important to + note that Vikings, a known vendor for libre-software-compatible hardware, does + not recommend using the Opteron 6100 series due to the lack of IOMMU support, + which is critical for security. Fortunately, AMD Family 15h + processors are also supported. However, the Opteron 6300 series, while + supported, requires proprietary microcode updates for stability, IOMMU + functionality, and fixes for specific vulnerabilities, including a gain-root- + via-NMI exploit. The Opteron 6200 series does not suffer from + these problems and works properly without any proprietary microcode update + needed \cite{vikings}. \\ + + \begin{figure}[H] + \centering + \includegraphics[width=0.9\textwidth]{images/opteron6200_annoté.png} + \caption{Annotated photography of an Opteron 6200 series CPU (2024), from a photography by AMD Inc. (2008)} + \label{fig:opteron2600} + \end{figure} + + The Opteron 6200 series, part of the Bulldozer microarchitecture, was designed to + target high-performance server applications. These processors feature 16 cores, + organized into 8 Bulldozer modules, with each module containing two integer cores + that shared resources like the floating-point unit (FPU) and L2 cache + (fig. \ref{fig:opteron2600}, \ref{fig:opteron2600_diagram}) + \cite{amd_6200}\cite{anandtech_bulldozer}. + + The architecture of the Opteron 6200 series is built around AMD's Bulldozer core + design, which uses Clustered Multithreading (CMT) to maximize resource + utilization. This is a technique where each processor + module contains two integer cores that share certain resources like the + floating-point unit (FPU), L2 cache, and instruction fetch/decode stages. Unlike + traditional multithreading, where each core handles multiple threads, CMT allows + two cores to share resources to improve parallel processing efficiency. This + approach aims to balance performance and resource usage, particularly in multi- + threaded workloads, though it can lead to some performance trade-offs in + single-threaded tasks. + In the Opteron 6272, the processor consists of eight modules, effectively + creating 16 integer cores. Due to the CMT architecture, each Opteron 6272 chip + functions as two CPUs within a single processor, each with its own set of cores, + L2 caches, and shared L3 cache. Here, one CPU is made by four modules, each + module in it sharing certain components, such as the FPU and L2 cache, between + two integer cores. The L3 cache is shared across these modules. + HyperTransport links provide high-speed communication between the two sockets of + the KGPE-D16. Shared L3 cache and direct memory access are provided by each + socket \cite{amd_6200}\cite{hill_impact_caching}. \\ + + This architecture also integrates a quad-channel DDR3 memory controller directly + into the processor die, which facilitates high bandwidth and low latency access + to memory. This memory controller supports DDR3 memory speeds up to 1600 MHz and + connects directly to the memory modules via the memory bus. By integrating the + memory controller into the processor, the Opteron 6200 series reduces memory + access latency, enhancing overall performance + \cite{amd_6200}Is \cite{amd_ddr3_guide}. It is interesting to note that Opterons + incorporate the internal northbridge that we cited previously. The traditional + northbridge functions, such as memory controller and PCIe interface management, + are partially integrated into the processor. This integration reduces the + distance data must travel between the CPU and memory, decreasing latency and + improving performance, particularly in memory-intensive applications + \cite{amd_6200}. \\ + + + \begin{figure}[H] + \centering + \includegraphics[width=0.8\textwidth]{ + images/fig3_img_dual_processor_node.png} + \caption{Functional diagram of an Opteron 6200 package (CC BY-SA 4.0, 2024)} + \label{fig:opteron2600_diagram} + \end{figure} + + Power efficiency was a key focus in the design of the Opteron 6200 series. + Despite the high core count, the processor includes several power management + features, such as Dynamic Power Management (DPM) and Turbo Core technology. These + features allow the processor to adjust power usage based on workload demands, + balancing performance with energy consumption. However, the Bulldozer + architecture's focus on high clock speeds and multi-threaded performance resulted + in higher power consumption compared to competing architectures + \cite{anandtech_bulldozer}. A special model of the series, + called \textit{high efficiency} models, solve a bit this problem by proposing + a bit less performant processor but with a power consumption divided by a factor + from 1.5 to 2.0 in some cases. \\ + + The processor connected to the I/O hub is known as the Bootstrap + Processor (BSP). + The BSP is responsible for starting up the system by executing the + initial firmware code from the reset vector, a specific memory address where the + CPU begins execution after a reset \cite{amd_bsp}. Core 0 of the BSP, called the + Bootstrap Core (BSC), initiates this process. During early initialization, the + BSP performs several critical tasks, such as memory initialization, and bringing + other CPU cores online. One of its duties is storing Built-In Self-Test (BIST) + information, which involves checking the integrity of the processor's internal + components to ensure they are functioning correctly. The BSP also determines the + type of reset that has occurred—whether it's a cold reset, which happens when + the system is powered on from an off state, or a warm reset, which is a restart + without turning off the power. Identifying the reset type is crucial for + deciding which initialization procedures need to be executed + \cite{amd_bsp}\cite{BKDG}. + + \section{Baseboard Management Controller} + + TODO + +\chapter{Key components in modern firmware} + + \section{General structure of coreboot} + + The firmware of the ASUS KGPE-D16 is crucial in ensuring the proper functioning + and optimization of the mainboard's hardware components. For this to be done + efficiently, \textit{coreboot} is organized in different stages (fig. + \ref{fig:coreboot_stages}) \cite{coreboot_docs}. + + \begin{figure}[H] + \centering + \includegraphics[width=0.9\textwidth]{ + images/fig9_coreboot_stages.png} + \caption{\textit{coreboot}'s stages timeline, by \textit{coreboot} project (CC BY-SA 4.0, 2009)} + \label{fig:coreboot_stages} + \end{figure} + + Being a complex project with ambitious goals, \textit{coreboot} decided early on + to establish an file-system-based architecture for its images (also called ROMs). + This special file-system is CBFS (which stands for coreboot file system). + The CBFS architecture consists of a binary image that can be interpreted as a + physical disk, referred to here as ROM. A number of independent components, each + with a header added to the data, are located within the ROM. The components are + nominally arranged sequentially, although they are aligned along a predefined + boundary \ref{fig:coreboot_diagram}). \\ + + Each stage is compiled as a separate binary and inserted into the CBFS with + custom compression. The \textbf{bootblock} is usually not compressed, while the + \textbf{ramstage} and the \textbf{payload} are compressed with LZMA. + Each stage loads the next stage at a given address (possibly decompressing it + in the process). \\ + + + \begin{figure}[H] + \centering + \includegraphics[width=0.8\textwidth]{ + images/fig8_coreboot_architecture.png} + \caption{\textit{coreboot} ROM architecture (CC BY-SA 4.0, 2024)} + \label{fig:coreboot_diagram} + \end{figure} + + Some stages are relocatable and can be placed anywhere in the RAM. These stages + are typically cached in the \textbf{CBMEM} for faster loading times during + wake-up. The CBMEM is a specific memory area used by the + \textit{coreboot} firmware to store important data structures and logs during the + boot process. This area is typically allocated in the system's RAM and is used to + store various types of runtime information that it might need to reference + after the initial boot stages. + + \subsection{Bootblock stage} + + The \textbf{bootblock} is the first stage executed after the CPU reset. + The beginning of this stage is written in assembly language, and its main task is + to set everything up for a C environment. The rest, of course, is written in C. + \\ + + The \textbf{bootblock} occupies the last 20k and within it is a main + header containing information about the ROM, including the size, component + alignment, and the offset of the start of the first CBFS component in the ROM. + This block is a mandatory component of the ROM as it also contains the entry + point of the firmware. \\ + + Upon startup, this stage is responsible for the initial hardware setup, which + involves identifying and configuring the CPU. This process is particularly + significant for AMD Family 10h/15h processors, where the firmware sets up the + Bootstrap Processor (BSP) and executes the necessary initialization routines. + Using the BSP, it enables the processor's cache, a small but fast type of memory + that stores frequently accessed data, improving overall system speed by reducing + data access time. However, the cache is there used as memory since DDR DIMMs are + not available yet. It is done by programing the \textbf{Memory Type Range + Registers} (MTRRs), which define how different ranges of system memory are + accessed, such as whether they are cacheable or non-cacheable, used to optimize + memory performance on normal operation. + The firmware will then set the stack pointer, allocate memory for the BSS, and + decompress and load the next stage. On x86 platforms, this process also includes + updating the CPU microcode, initializing the timer, and transitioning from 16-bit + real mode to 32-bit protected mode. The \textbf{bootblock} is responsible for + loading the romstage, or the verstage if verified boot is enabled. + + \subsection{Romstage} + + The firmware also configures the Advanced Programmable Interrupt Controller + (APIC), which manages how the processor handles interrupts to ensure + the system can respond efficiently to hardware and + software events. Lastly, it sets up the routing for HyperTransport (HT) + technology, a high-speed communication protocol used for data exchange between + the processor and the northbridge, ensuring that data flows smoothly + between these components. + Memory training and optimization are key functions of the firmware. During this + process, the firmware adjusts memory settings, such as timings, frequencies, and + voltages, to ensure that the installed memory modules operate efficiently and + stably. This step is crucial for achieving optimal performance, especially when + dealing with large amounts of RAM for a large amount of CPU cores, as + supported by the KGPE-D16. \\ + + \subsection{Ramstage} + + Effective resource allocation is essential for system stability, particularly in + complex configurations involving multiple CPUs and peripherals. The firmware + manages resource allocation, resolving any conflicts between hardware components + to prevent resource contention and ensure smooth operation. \\ + + Power management is another critical aspect managed by the firmware. Through the + Advanced Configuration and Power Interface (ACPI), the firmware can adjust the + power states of various components, optimizing energy consumption across the + system. This not only reduces power usage but also minimizes heat generation, + which is vital for maintaining system longevity and efficiency. \\ + + Security is a major concern in modern systems, and the KGPE-D16’s firmware + includes features designed to protect the system from unauthorized access and + maintain the integrity of its operations. This includes support for IOMMU, which + is crucial for preventing unauthorized direct memory access (DMA) attacks, + particularly in virtualized environments. + + \subsection{Payload} + + TODO + + \section{Advanced Configuration and Power Interface} + + The Advanced Configuration and Power Interface (ACPI) is a critical component + of modern computing systems, providing an open standard for device + configuration and power management by the operating system (OS). Developed in + 1996 by Intel, Microsoft, and Toshiba, ACPI replaced the older Advanced Power + Management (APM) standard with more advanced and flexible power management + capabilities\cite{intel_acpi_spec}. + At its core, ACPI is implemented through a series of data structures and + executable code known as ACPI tables, which are provided by the system firmware + and interpreted by the OS. These tables describe various aspects of the system, + including hardware resources, device power states, and thermal zones. The ACPI + Specification outlines these structures and provides the necessary + standardization for interoperability across different platforms and operating + systems\cite{acpi_os_support}. These tables are used by the OS to perform + low-level task, including managing power states of the CPU, controlling the + voltage and frequency scaling (also known as Dynamic Voltage and Frequency + Scaling, or DVFS), and coordinating power delivery to peripherals. \newline + + The ACPI Component Architecture (ACPICA) is the reference implementation of + ACPI, providing a common codebase that can be used by OS developers to + integrate ACPI support. ACPICA includes tools and libraries that allow for the + parsing and execution of ACPI Machine Language (AML) code, which is embedded + within the ACPI tables\cite{acpi_programming}. One of the key tools in ACPICA + is the Intel ACPI Source Language (IASL) compiler, which converts ACPI Source + Language (ASL) code into AML bytecode, allowing firmware developers to write + custom ACPI methods\cite{intel_acpi_spec}. + The triggering of ACPI events is managed through a combination of hardware + signals and software routines. For example, when a user presses the power + button on a system, an ACPI event is generated, which is then handled by the + OS. This event might trigger the system to enter a low-power state, such as + sleep or hibernation, depending on the configuration provided by the ACPI + tables\cite{acpi_os_support}. These power states are defined in the ACPI + specification, with global states (G0 to G3) representing different levels of + system power consumption, and device states (D0 to D3) representing individual + device power levels. \newline + + \textbf{ASUS KGPE-D16 Example}: The ASUS KGPE-D16 mainboard, which is designed + for server and high-performance computing environments, utilizes ACPI for + managing its power distribution across multiple CPUs and attached peripherals. + ACPI is integral in controlling the power states of various components, thereby + optimizing performance and energy use. Additionally, the firmware on the + KGPE-D16 uses ACPI tables to manage system temperature and fan speed, ensuring + reliable operation under heavy workloads\cite{ASUS_kgpe_d16_manual}. + + \section{System Management Mode} + + System Management Mode (SMM) is a highly privileged operating mode provided by + x86 processors for handling system-level functions such as power management, + hardware control, and other critical tasks that must be isolated from the OS + and applications. Introduced by Intel, SMM operates in an environment separate + from the main operating system, offering a secure and controlled space for + executing sensitive operations\cite{uefi_smm_security}. \newline + + SMM is triggered by a System Management Interrupt (SMI), which is a + non-maskable interrupt that causes the CPU to save its current state and switch + to executing code stored in a protected area of memory called System Management + RAM (SMRAM). SMRAM is a specialized memory region that is isolated from the + rest of the system, making it inaccessible to the OS and preventing tampering + or interference from other software\cite{heasman2007}. Within SMM, the + firmware can execute various low-level functions that require direct hardware + control or need to be protected from the OS. This includes tasks such as + thermal management, where the system monitors CPU temperature and adjusts + performance or power levels to prevent overheating, as well as power management + routines that enable efficient energy usage by adjusting power states based on + system activity\cite{offsec_bios_smm}. + One of the critical security features of SMM is its role in managing firmware + updates and handling system-level security events. Because SMM operates in a + privileged mode that is isolated from the OS, it can securely apply firmware + updates and respond to security threats without being affected by potentially + compromised system software\cite{domas2015}. However, the high privilege level + and isolation of SMM also present significant security challenges. If an + attacker can compromise SMM, they gain full control over the system, bypassing + all security measures implemented by the OS\cite{cyber_smm_hack}. \newline + + \textbf{ASUS KGPE-D16 Example}: The ASUS KGPE-D16 mainboard utilizes SMM to + perform critical management tasks that need to be isolated from the operating + system. For example, SMM is used to monitor and manage system health by + responding to thermal events and adjusting power levels to maintain system + stability. SMM operates independently of the main operating system, allowing it + to perform sensitive tasks securely. + \textit{coreboot}, an open-source firmware project, supports SMM, but its + implementation + is typically minimal compared to traditional BIOS/UEFI systems. + In \textit{coreboot}, SMM initialization involves setting up the System Management + Interrupt (SMI) handler and configuring System Management RAM (SMRAM), the + memory region where SMM code executes\cite{brown2003linuxbios}. The extent of + SMM support in \textit{coreboot} can vary significantly depending on the hardware + platform and the specific requirements of the system. \textit{coreboot}'s design + philosophy emphasizes a lightweight and fast boot process, delegating more + complex management tasks to payloads or the operating system itself + \cite{reinauer2008coreboot}. + + One of the key challenges with implementing SMM in \textit{coreboot} is ensuring + that + SMI handlers are configured correctly to manage necessary system tasks without + compromising security or performance. \textit{coreboot}'s approach to SMM is + consistent + with its overall goal of providing a streamlined and efficient firmware + solution, leaving more intricate functionalities to be handled by subsequent + software layers\cite{mohr2012comparative}. + + \section{AMD Platform Security Processor and Intel Management Engine} + + The AMD Platform Security Processor (PSP) and Intel Management Engine (ME) are + embedded subsystems within AMD and Intel processors, respectively, that handle + a range of security-related tasks independent of the main CPU. These + subsystems are fundamental to the security architecture of modern computing + platforms, providing functions such as secure boot, cryptographic key + management, and remote system management\cite{amd_psp_overview}. + The AMD PSP is based on an ARM Cortex-A5 processor and is responsible for + several security functions, including the validation of firmware during boot + (secure boot), management of Trusted Platform Module (TPM) functions, and + handling cryptographic operations such as key generation and storage. The PSP + operates independently of the main x86 cores, which allows it to execute + security functions even when the main system is powered off or compromised by + malware\cite{amd_psp_overview}. The PSP's isolated environment ensures that + sensitive operations are protected from threats that could affect the main OS. + + Similarly, the Intel Management Engine (ME) is a dedicated microcontroller + embedded within Intel chipsets that operates independently of the main CPU. + The ME is a comprehensive subsystem that provides a variety of functions, + including out-of-band system management, security enforcement, and support for + Digital Rights Management (DRM) \cite{intel_csme}. The ME's firmware runs on an + isolated environment that allows it to perform these tasks securely, even when + the system is powered off. This capability is crucial for enterprise + environments where administrators need to perform remote diagnostics, updates, + and security checks without relying on the main OS. \newline + + The Intel ME, however, has been a source of controversy due to its deep + integration into the hardware and its potential to be exploited if + vulnerabilities are discovered. Researchers have demonstrated ways to hack into + the ME, potentially gaining control over a system even when it is powered off + \cite{blackhat_me_hack}. These concerns have led to calls for greater + transparency and security measures around the ME and similar subsystems. + When comparing Intel ME and AMD PSP, the primary difference lies in their scope + and functionality. Intel ME offers more extensive remote management + capabilities, making it a more comprehensive tool for enterprise environments, + while AMD PSP focuses more narrowly on core security tasks. Nonetheless, both + play critical roles in ensuring the security and integrity of modern computing + systems. \newline + + \textbf{ASUS KGPE-D16 Example}: The ASUS KGPE-D16 mainboard does not include + the AMD Platform Security Processor (PSP) or the Intel ME. + +\chapter{Memory initialization and training algorithms} + + \section{Importance of memory initialization} \begin{itemize} \item Steps involved in initializing the memory controller \item Critical role in system stability and performance - \item \textbf{Asus KGPE-D16 Example}: Memory initialization process on the KGPE-D16 mainboard + \item \textbf{ASUS KGPE-D16 Example}: Memory initialization process on the KGPE-D16 mainboard \end{itemize} Memory training involves several steps: + 1. **Detection and Initialization**: The BIOS detects the installed memory modules, determining their size, speed, and type. + 2. **Configuration and Timing Setup**: The BIOS configures the memory controller settings, including timings for memory access such as CAS - latency, RAS to CAS delay, and other parameters \cite{intel_uefi}. + latency, RAS to CAS delay, and other parameters\cite{intel_uefi}. + 3. **Training and Calibration**: The BIOS performs tests and adjustments to calibrate the memory system, ensuring stable operation at optimal speeds by - adjusting signal voltages and testing data integrity \cite{wolf2006}. + adjusting signal voltages and testing data integrity\cite{wolf2006}. These steps are crucial for modern systems, where improper memory configuration can lead to instability, data corruption, or suboptimal @@ -426,22 +927,22 @@ firmware solutions to ensure greater control and security in computing. predefined profiles and dynamic adjustments to achieve the best balance between speed and stability. Advanced timing optimization involves setting these parameters to ensure that memory operations are performed with - minimal latency and maximum throughput \cite{russinovich2012}. + minimal latency and maximum throughput\cite{russinovich2012}. - \section{Memory Training Algorithms} + \section{Memory training algorithms} \begin{itemize} \item Techniques used for training memory \item Optimization of timings and voltage settings \item Challenges in multi-core CPU environments - \item \textbf{Asus KGPE-D16 Example}: Specific algorithms used for memory training in the mainboard and their performance outcomes + \item \textbf{ASUS KGPE-D16 Example}: Specific algorithms used for memory training in the mainboard and their performance outcomes \end{itemize} To optimize memory performance, the BIOS employs various training algorithms and calibration techniques. These methods test the memory under different conditions and make necessary adjustments to improve stability and efficiency. Key techniques include voltage adjustments, data integrity - testing, and signal timing calibration \cite{shin2011}. + testing, and signal timing calibration\cite{shin2011}. Voltage adjustments involve tweaking the power supplied to the memory modules to ensure reliable operation. Data integrity testing checks that @@ -449,58 +950,59 @@ firmware solutions to ensure greater control and security in computing. fine-tunes the delays between different memory operations to minimize latency. - \section{Practical Examples} + \section{Practical examples} \begin{itemize} \item Real-world scenarios where firmware played a crucial role in system performance \item Analysis of firmware updates and their impact on the KGPE-D16 mainboard \item User experiences and testimonials highlighting the importance of firmware - \item \textbf{Asus KGPE-D16 Example}: Specific case studies and firmware updates for the mainboard + \item \textbf{ASUS KGPE-D16 Example}: Specific case studies and firmware updates for the mainboard \end{itemize} -\chapter{Firmware and Hardware Virtualization} +\chapter{Firmware and hardware virtualization} - \section{Introduction to Hardware Virtualization} + \section{Introduction to hardware virtualization} \begin{itemize} \item Definition and purpose of virtualization \item How firmware interacts with virtualized environments - \item \textbf{Asus KGPE-D16 Example}: Virtualization capabilities and performance on the mainboard + \item \textbf{ASUS KGPE-D16 Example}: Virtualization capabilities and performance on the mainboard \end{itemize} - \section{Role of BIOS/UEFI in Virtualization} + \section{Role of BIOS/UEFI in virtualization} \begin{itemize} \item Initialization and configuration for virtual machines \item Resource allocation and management - \item \textbf{Asus KGPE-D16 Example}: BIOS/UEFI settings and their impact on virtualization efficiency on the KGPE-D16 + \item \textbf{ASUS KGPE-D16 Example}: BIOS/UEFI settings and their impact on virtualization efficiency on the KGPE-D16 \end{itemize} \section{Security and freedom considerations} \begin{itemize} \item Security risks associated with virtualization \item Measures taken by firmware to mitigate risks - \item \textbf{Asus KGPE-D16 Example}: Security measures implemented in the mainboard's firmware to support secure virtualization + \item \textbf{ASUS KGPE-D16 Example}: Security measures implemented in the mainboard's firmware to support secure virtualization \end{itemize} - \section{Future Trends in Firmware and Virtualization} + \section{Future trends in firmware and virtualization} \begin{itemize} \item Emerging advancements and their impact on firmware \item Predictions for the evolution of BIOS/UEFI in virtualization - \item \textbf{Asus KGPE-D16 Example}: Potential future firmware updates and their expected impact on the mainboard's virtualization capabilities + \item \textbf{ASUS KGPE-D16 Example}: Potential future firmware updates and their expected impact on the mainboard's virtualization capabilities \end{itemize} \chapter*{Conclusion} \addcontentsline{toc}{chapter}{Conclusion} - \section{Summary of Key Points} + \section{Summary of key points} \begin{itemize} \item Recap of the evolution and current state of firmware \item Importance of understanding modern BIOS functionalities - \item \textbf{Asus KGPE-D16 Example}: Summary of the mainboard's features and firmware contributions + \item \textbf{ASUS KGPE-D16 Example}: Summary of the mainboard's features and firmware contributions \end{itemize} - \section{Call for Action} + \section{Call for action} \begin{itemize} \item Advocacy for free software-compatible hardware \item Encouraging research and development in libre firmware solutions + \item A libre BIOS is very important\cite{coreboot_fsf}. \end{itemize} \newpage diff --git a/hardware_init_review.toc b/hardware_init_review.toc index 9b04322..35886a7 100644 --- a/hardware_init_review.toc +++ b/hardware_init_review.toc @@ -3,29 +3,36 @@ \contentsline {chapter}{\numberline {1}Introduction to firmware and BIOS evolution}{5}{chapter.1}% \contentsline {section}{\numberline {1.1}Historical context of BIOS}{5}{section.1.1}% \contentsline {subsection}{\numberline {1.1.1}Definition and origin}{5}{subsection.1.1.1}% -\contentsline {subsection}{\numberline {1.1.2}Functionalities and limitations}{5}{subsection.1.1.2}% -\contentsline {section}{\numberline {1.2}Modern BIOS and UEFI}{6}{section.1.2}% -\contentsline {subsection}{\numberline {1.2.1}Transition from traditional BIOS to UEFI (Unified Extensible Firmware Interface)}{6}{subsection.1.2.1}% -\contentsline {subsection}{\numberline {1.2.2}An other way with coreboot}{7}{subsection.1.2.2}% -\contentsline {section}{\numberline {1.3}Shift in firmware responsibilities}{7}{section.1.3}% -\contentsline {chapter}{\numberline {2}Characteristics of Asus KGPE-D16 Mainboard}{9}{chapter.2}% -\contentsline {section}{\numberline {2.1}Overview of Asus KGPE-D16 Hardware}{9}{section.2.1}% -\contentsline {section}{\numberline {2.2}Firmware's Role in Asus KGPE-D16}{9}{section.2.2}% -\contentsline {chapter}{\numberline {3}Key Components in Modern Firmware}{10}{chapter.3}% -\contentsline {section}{\numberline {3.1}Advanced Configuration and Power Interface (ACPI)}{10}{section.3.1}% -\contentsline {section}{\numberline {3.2}System Management Mode (SMM)}{10}{section.3.2}% -\contentsline {section}{\numberline {3.3}AMD Platform Security Processor (PSP) and Intel Management Engine (ME)}{10}{section.3.3}% -\contentsline {chapter}{\numberline {4}Memory Initialization and Training Algorithms}{11}{chapter.4}% -\contentsline {section}{\numberline {4.1}Importance of Memory Initialization}{11}{section.4.1}% -\contentsline {section}{\numberline {4.2}Memory Training Algorithms}{11}{section.4.2}% -\contentsline {section}{\numberline {4.3}Practical Examples}{12}{section.4.3}% -\contentsline {chapter}{\numberline {5}Firmware and Hardware Virtualization}{13}{chapter.5}% -\contentsline {section}{\numberline {5.1}Introduction to Hardware Virtualization}{13}{section.5.1}% -\contentsline {section}{\numberline {5.2}Role of BIOS/UEFI in Virtualization}{13}{section.5.2}% -\contentsline {section}{\numberline {5.3}Security and freedom considerations}{13}{section.5.3}% -\contentsline {section}{\numberline {5.4}Future Trends in Firmware and Virtualization}{13}{section.5.4}% -\contentsline {chapter}{Conclusion}{14}{chapter*.2}% -\contentsline {section}{\numberline {5.5}Summary of Key Points}{14}{section.5.5}% -\contentsline {section}{\numberline {5.6}Call for Action}{14}{section.5.6}% -\contentsline {chapter}{Bibliography}{15}{section.5.6}% -\contentsline {chapter}{GNU Free Documentation License}{18}{chapter*.4}% +\contentsline {subsection}{\numberline {1.1.2}Functionalities and limitations}{6}{subsection.1.1.2}% +\contentsline {section}{\numberline {1.2}Modern BIOS and UEFI}{7}{section.1.2}% +\contentsline {subsection}{\numberline {1.2.1}Transition from traditional BIOS to UEFI (Unified Extensible Firmware Interface)}{7}{subsection.1.2.1}% +\contentsline {subsection}{\numberline {1.2.2}An other way with \textit {coreboot}}{7}{subsection.1.2.2}% +\contentsline {section}{\numberline {1.3}Shift in firmware responsibilities}{9}{section.1.3}% +\contentsline {chapter}{\numberline {2}Characteristics of ASUS KGPE-D16 mainboard}{10}{chapter.2}% +\contentsline {section}{\numberline {2.1}Overview of ASUS KGPE-D16 hardware}{11}{section.2.1}% +\contentsline {section}{\numberline {2.2}Chipset}{12}{section.2.2}% +\contentsline {section}{\numberline {2.3}Processors}{14}{section.2.3}% +\contentsline {section}{\numberline {2.4}Baseboard Management Controller}{15}{section.2.4}% +\contentsline {chapter}{\numberline {3}Key components in modern firmware}{16}{chapter.3}% +\contentsline {section}{\numberline {3.1}General structure of coreboot}{16}{section.3.1}% +\contentsline {subsection}{\numberline {3.1.1}Bootblock stage}{17}{subsection.3.1.1}% +\contentsline {subsection}{\numberline {3.1.2}Romstage}{17}{subsection.3.1.2}% +\contentsline {subsection}{\numberline {3.1.3}Ramstage}{18}{subsection.3.1.3}% +\contentsline {subsection}{\numberline {3.1.4}Payload}{18}{subsection.3.1.4}% +\contentsline {section}{\numberline {3.2}Advanced Configuration and Power Interface}{18}{section.3.2}% +\contentsline {section}{\numberline {3.3}System Management Mode}{19}{section.3.3}% +\contentsline {section}{\numberline {3.4}AMD Platform Security Processor and Intel Management Engine}{19}{section.3.4}% +\contentsline {chapter}{\numberline {4}Memory initialization and training algorithms}{21}{chapter.4}% +\contentsline {section}{\numberline {4.1}Importance of memory initialization}{21}{section.4.1}% +\contentsline {section}{\numberline {4.2}Memory training algorithms}{21}{section.4.2}% +\contentsline {section}{\numberline {4.3}Practical examples}{21}{section.4.3}% +\contentsline {chapter}{\numberline {5}Firmware and hardware virtualization}{23}{chapter.5}% +\contentsline {section}{\numberline {5.1}Introduction to hardware virtualization}{23}{section.5.1}% +\contentsline {section}{\numberline {5.2}Role of BIOS/UEFI in virtualization}{23}{section.5.2}% +\contentsline {section}{\numberline {5.3}Security and freedom considerations}{23}{section.5.3}% +\contentsline {section}{\numberline {5.4}Future trends in firmware and virtualization}{23}{section.5.4}% +\contentsline {chapter}{Conclusion}{24}{chapter*.2}% +\contentsline {section}{\numberline {5.5}Summary of key points}{24}{section.5.5}% +\contentsline {section}{\numberline {5.6}Call for action}{24}{section.5.6}% +\contentsline {chapter}{Bibliography}{25}{section.5.6}% +\contentsline {chapter}{GNU Free Documentation License}{30}{chapter*.4}%