diff --git a/hardware_init_review.tex b/hardware_init_review.tex
index e9ce2c3..02e7d9b 100644
--- a/hardware_init_review.tex
+++ b/hardware_init_review.tex
@@ -2657,17 +2657,8 @@ if (Pass == FirstPass) {
                     \label{lst:write_level_first_pass}
                 \end{listing}
 
-            \subsubsection{Details on the write leveling implementation}
-
-                \subsection{Write Leveling on AMD Fam15h G34 Processors with RDIMMs}
-
-                    Write leveling is a crucial process in memory initialization
-                    for DDR3 systems, ensuring that the DQS signals are
-                    correctly aligned with the clock signals during write
-                    operations. This is particularly important in systems using
-                    AMD Fam15h processors with G34 sockets and RDIMM. The
-                    write leveling process is divided into three distinct
-                    phases, each managed by a specific function:
+                    The detailled write leveling process is divided into three
+                    distinct phases, each managed by a specific function:
                     \path{AgesaHwWlPhase1}, \path{AgesaHwWlPhase2}, and
                     \path{AgesaHwWlPhase3} from \path{mcthwl.c}.
                     These phases work together to