% -*- coding: utf-8 -*- % Copyright (C) 2024 Adrien 'neox' Bourmault % % Permission is granted to copy, distribute and/or modify this document % under the terms of the GNU Free Documentation License, Version 1.3 % or any later version published by the Free Software Foundation; % with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. % A copy of the license is included in the section entitled "GNU % Free Documentation License". \input{packages.tex} % setup things \setcounter{secnumdepth}{4} \setcounter{tocdepth}{4} %\setcounter{secnumdepth}{4} % setup bibliography \addbibresource{bibliographie.bib} % ------------------------------------------------------------------------------ \begin{document}{ % ------------------------------------------------------------------------------ \sloppy % allow flexible margins \input{titlepage.tex} % import titlepage \newpage % -------------------------------------------------------------------------------------- % License header % -------------------------------------------------------------------------------------- \setcounter{page}{2} \vspace*{\fill} % fill the page so that text is at the bottom This is Edition 0.0. \\ Copyright (C) 2024 Adrien 'neox' Bourmault \href{mailto:neox@gnu.org}{} \\ Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". \newpage % Table of contents \tableofcontents \newpage \chapter*{Abstract} \addcontentsline{toc}{chapter}{Abstract} The global trend is towards the scarcity of free software-compatible hardware, and soon there will be no computer that will work without software domination by big companies, especially involving firmware like BIOSes. \\ A Basic Input Output System (BIOS) was originally a set of low-level functions contained in the read-only memory of a computer's mainboard, enabling it to perform basic operations when powered up. However, the definition of a BIOS has evolved to include what used to be known as Power On Self Test (POST) for the presence of peripherals, allocating resources for them to avoid conflicts, and then handing over to an operating system boot loader. Nowadays, the bulk of the BIOS work is the initialization and training of RAM. This means, for example, initializing the memory controller and optimizing timing and read/write voltage for optimal performance, making the code complex, as its role is to optimize several parallel buses operating at high speeds and shared by many CPU cores, and make them act as a homogeneous whole. \\ This document is the product of a project hosted by the \textit{LIP6 laboratory} and supported by the \textit{GNU Boot Project} and the \textit{Free Software Foundation}. It delves into the importance of firmware in the hardware initialization of modern computers and explores various aspects of firmware, such as Intel Management Engine (ME), AMD Platform Security Processor (PSP), Advanced Configuration and Power Interface (ACPI), and System Management Mode (SMM). Additionally, it provides an in-depth look at memory initialization and training algorithms, highlighting their critical role in system stability and performance. Examples of the implementation in the ASUS KGPE-D16 mainboard are presented, describing its hardware characteristics, topology, and the crucial role of firmware in its operation after the mainboard architecture is examined. Practical examples illustrate the impact of firmware on hardware initialization, memory optimization, resource allocation, power management, and security. Specific algorithms used for memory training and their outcomes are analyzed to demonstrate the complexity and importance of firmware in achieving optimal system performance. Furthermore, this document explores the relationship between firmware and hardware virtualization. Security considerations and future trends in firmware development are also addressed, emphasizing the need for continued research and advocacy for free software-compatible hardware. \chapter{Introduction to firmware and BIOS evolution} \section{Historical context of BIOS} \subsection{Definition and origin} The BIOS (Basic Input/Output System) is firmware, which is a type of software that is embedded into hardware devices to control their basic functions, acting as a bridge between hardware and other software, ensuring that the hardware operates correctly. Unlike regular software, firmware is usually stored in a non-volatile memory like ROM or flash memory. The term "firmware" comes from its role: it is "firm" because it's more permanent than regular software (which can be easily changed) but not as rigid as hardware. \\ The BIOS is used to perform initialization during the booting process and to provide runtime services for operating systems and programs. Being a critical component for the startup of personal computers, acting as an intermediary between the computer's hardware and its operating system, the BIOS is embedded on a chip on the motherboard and is the first code that runs when a PC is powered on. The concept of BIOS has its roots in the early days of personal computing. It was first developed by IBM for their IBM PC, which was introduced in 1981 \cite{freiberger2000fire}. The term BIOS itself was coined by Gary Kildall, who developed the CP/M (Control Program for Microcomputers) operating system \cite{shustek2016kildall}. In CP/M, BIOS was used to describe a component that interfaced directly with the hardware, allowing the operating system to be somewhat hardware-independent. \\ \begin{figure}[H] \centering \includegraphics[width=0.5\textwidth]{images/IBM_logo.png} \caption{The eight-striped wordmark of IBM (1967, public domain, trademarked)} \end{figure} IBM's implementation of BIOS became a de facto standard in the industry, as it was part of the IBM PC's open architecture \cite{grewal_ibm_pc}\cite{ibm_pc}, which refers to the design philosophy adopted by IBM when developing the IBM Personal Computer (PC), introduced in 1981. This architecture is characterized by the use of off-the-shelf components and publicly available specifications, which allowed other manufacturers to create compatible hardware and software. It was in fact a departure from the proprietary systems prevalent at the time, where companies closely guarded their designs to maintain control over the hardware and software ecosystem. For example, IBM used the Intel 8088 CPU, a well-documented and widely available processor, and also the Industry Standard Architecture (ISA) bus, which defined how various components like memory, storage, and peripherals communicated with the CPU. This open architecture allowed other manufacturers to create IBM-compatible computers, also known as "clones", which further popularized the BIOS concept. As a result, the IBM PC BIOS set the stage for a standardized method of interacting with computer hardware, which has evolved over the years but remains fundamentally the same in principle. IBM also published detailed technical documentation at that time, including circuit diagrams, BIOS listings, and interface specifications. This transparency allowed other companies to understand and replicate the IBM PC's functionality \cite{freiberger2000fire}. \subsection{Functionalities and limitations} When a computer is powered on, the BIOS executes a Power-On Self-Test (POST), a diagnostic sequence that verifies the integrity and functionality of critical hardware components such as the CPU, RAM, disk drives, keyboard, and other peripherals \cite{wiki_bios}. This process ensures that all essential hardware components are operational before the system attempts to load the operating system. If any issues are detected, the BIOS generates error messages or beep codes to alert the user. Following the successful completion of POST, the BIOS runs the bootstrap loader, a small program that identifies the operating system's bootloader on a storage device, such as a hard drive, floppy disk, or optical drive. The bootstrap loader then transfers control to the OS bootloader, initiating the process of loading the operating system into the computer's memory and starting it. This step effectively bridges the gap between hardware initialization and operating system execution. The BIOS also provides a set of low-level software routines known as interrupts. These routines enable software to perform basic input/output operations, such as reading from the keyboard, writing to the display, and accessing disk drives, without needing to manage the hardware directly. By providing standardized interfaces for hardware components, the BIOS simplifies software development and improves compatibility across different hardware configurations \cite{ibm_pc}. \\ \begin{figure}[H] \centering \includegraphics[width=0.5\textwidth]{images/bios_chip.jpg} \caption{An AMI BIOS chip from a Dell 310, by Jud McCranie (CC BY-SA 4.0, 2018)} \end{figure} Despite its essential role, the early BIOS had several limitations. One significant limitation was its limited storage capacity. Early BIOS firmware was stored in Read-Only Memory (ROM) chips with very limited storage, often just a few kilobytes. This constrained the complexity and functionality of the BIOS, limiting it to only the most essential tasks needed to start the system and provide basic hardware control. The original BIOS was also non-extensible. ROM chips were typically soldered onto the motherboard, making updates difficult and costly. Bug fixes, updates for new hardware support, or enhancements required replacing the ROM chip, leading to challenges in maintaining and upgrading systems. Furthermore, the early BIOS was tailored for the specific hardware configurations of the initial IBM PC models, which included a limited set of peripherals and expansion options. As new hardware components and peripherals were developed, the BIOS often needed to be updated to support them, which was not always feasible or timely. Performance bottlenecks were another limitation. The BIOS provided basic input/output operations that were often slower than direct hardware access methods. For example, disk I/O operations through BIOS interrupts were slower compared to later direct access methods provided by operating systems, resulting in performance bottlenecks, especially for disk-intensive operations. This inflexibility restricts the ability to support new hardware and technologies efficiently\cite{anderson_2018}. Early BIOS implementations also had minimal security features. There were no mechanisms to verify the integrity of the BIOS code or to protect against unauthorized modifications, leaving systems vulnerable to attacks that could alter the BIOS and potentially compromise the entire system, such as rootkits and firmware viruses. Added to that, the traditional BIOS operates in 16-bit real mode, a constraint that limits the amount of code and memory it can address. This limitation hinders the performance and complexity of firmware, making it less suitable for modern computing needs \cite{intel_uefi}. Additionally, BIOS relies on the Master Boot Record (MBR) partitioning scheme, which supports a maximum disk size of 2 terabytes and allows only four primary partitions \cite{uefi_spec}\cite{russinovich2012}. This constraint has become a significant drawback as storage capacities have increased. Furthermore, the traditional BIOS has limited flexibility and is challenging to update or extend. This inflexibility restricts the ability to support new hardware and technologies efficiently \cite{anderson_2018}\cite{acmcs2015}. \section{Modern BIOS and UEFI} \subsection{Transition from traditional BIOS to UEFI (Unified Extensible Firmware Interface)} All the limitations listed earlier caused a transition to a more modern firmware interface, designed to address the shortcomings of the traditional BIOS. This section delves into the historical context of this shift, the driving factors behind it, and the advantages UEFI offers over the traditional BIOS. \\ The development of UEFI began in the mid-1990s as part of the Intel Boot Initiative, which aimed to modernize the boot process and overcome the limitations of the traditional BIOS. By 2005, the Unified EFI Forum, a consortium of technology companies including Intel, AMD, and Microsoft, had formalized the UEFI specification \cite{uefi_spec}. UEFI was designed to address the shortcomings of the traditional BIOS, providing several key improvements. \begin{figure}[H] \centering \includegraphics[width=0.25\textwidth]{images/uefi_logo.png} \caption{The UEFI logo (public domain, 2010)} \end{figure} One of the most significant advancements of UEFI is its support for 32-bit and 64-bit modes, allowing it to address more memory and run more complex firmware programs. This capability enables UEFI to handle the increased demands of modern hardware and software \cite{intel_uefi}\cite{shin2011}. Additionally, UEFI uses the GUID Partition Table (GPT) instead of the MBR, supporting disks larger than 2 terabytes and allowing for a nearly unlimited number of partitions \cite{microsoft_uefi}\cite{russinovich2012}. Improved boot performance is another driving factor. UEFI provides faster boot times compared to the traditional BIOS, thanks to its efficient hardware and software initialization processes. This improvement is particularly beneficial for systems with complex hardware configurations, where quick boot times are essential \cite{intel_uefi}. UEFI's modular architecture makes it more extensible and easier to update compared to the traditional BIOS. This design allows for the addition of drivers, applications, and other components without requiring a complete firmware overhaul, providing greater flexibility and adaptability to new technologies \cite{acmcs2015}. UEFI also includes enhanced security features such as \textit{Secure Boot}, which ensures that only trusted software can be executed during the boot process, thereby protecting the system from unauthorized modifications and malware \cite{anderson_2018}\cite{chang2013}. \\ The industry-wide support and standardization of UEFI have accelerated its adoption across various platforms and devices. Major industry players, including Intel, AMD, and Microsoft, have adopted UEFI as the new standard for firmware interfaces, ensuring broad compatibility and interoperability \cite{uefi_spec}. \subsection{An other way with \textit{coreboot}} While UEFI has become the dominant firmware interface for modern computing systems, it is not without its critics. Some of the primary concerns about UEFI include its complexity, potential security vulnerabilities, and the degree of control it provides to hardware manufacturers over the boot process. Originally known as LinuxBIOS, \textit{coreboot}, is a free firmware project initiated in 1999 by Ron Minnich and his team at the Los Alamos National Laboratory. The project's primary goal was to create a fast, lightweight, and flexible firmware solution that could initialize hardware and boot operating systems quickly, while remaining transparent and auditable\cite{coreboot}. As an alternative to UEFI, \textit{coreboot} offers a different approach to firmware that aims to address some of these concerns and continue the evolution of BIOS.\\ One of the main advantages of \textit{coreboot} over UEFI is its simplicity, as it is designed to perform only the minimal tasks required to initialize hardware and pass control to a payload, such as a bootloader or operating system kernel. This minimalist approach reduces the attack surface and potential for security vulnerabilities, as there is less code that could be exploited by malicious actors \cite{rudolph2007}. Another significant benefit of \textit{coreboot} is its libre nature. Unlike UEFI, which is controlled by a consortium of hardware and software vendors, \textit{coreboot}'s source code is freely available and can be audited, modified, and improved by anyone. This transparency ensures that security researchers and developers can review the code for potential vulnerabilities and contribute to its improvement, fostering a community-driven approach to firmware development\cite{coreboot}. This project also supports a wide range of bootloaders, called payloads, allowing users to customize their boot process to suit their specific needs. Popular payloads include SeaBIOS, which provides legacy BIOS compatibility, and Tianocore, which offers UEFI functionality within the \textit{coreboot} framework. This flexibility allows \textit{coreboot} to be used in a variety of environments, from embedded systems to high-performance servers \cite{coreboot_payloads}. \\ \begin{figure}[H] \centering \includegraphics[width=0.3\textwidth]{images/coreboot_logo.png} \caption{The \textit{coreboot} logo, by Konsult Stuge \& coresystems (coreboot logo license, 2008)} \end{figure} Despite its advantages, \textit{coreboot} is not without its challenges. The project relies heavily on community contributions, and support for new hardware often lags behind that of UEFI. Additionally, the minimalist design of \textit{coreboot} means that some advanced features provided by UEFI are not available by default. However, the \textit{coreboot} community continues to work on adding new features and improving compatibility with modern hardware or security issues \cite{coreboot_challenges}. For example, it provides a \textit{verified boot} function, allowing to prevent rootkits and other attacks based on firmware modifications \cite{coreboot_docs}. However, it's important to note that \textit{coreboot} is not entirely free in all aspects. Many modern processors and chipsets require \textit{proprietary blobs}, short for \textit{Binary Large Object}, which is a collection of binary data stored as a single entity. These blobs are necessary for \textit{coreboot} to function correctly on a wide range of hardware, but they compromise the goal of having a fully free firmware one day \cite{blobs}, since these blobs are used for certain functionalities such as memory initialization and hardware management. \begin{figure}[H] \centering \includegraphics[width=0.25\textwidth]{images/gnuboot.png} \caption{The \textit{GNU Boot} logo, by Jason Self (CC0, 2020)} \end{figure} To address these concerns, the GNU Project has developed GNU Boot, a fully free distribution of firmware, including \textit{coreboot}, that aims to be entirely free by avoiding the use of proprietary binary blobs. GNU Boot is committed to using only free software for all aspects of firmware, making it a preferred choice for users and organizations that prioritize software freedom and transparency \cite{gnuboot}. \section{Shift in firmware responsibilities} Initially, the BIOS's primary function was to perform the POST, a basic diagnostic testing process to check the system's hardware components and ensure they were functioning correctly. This included verifying the CPU, memory, and essential peripherals before passing control to the operating system's bootloader. This process was relatively simple, given the limited capabilities and straightforward architecture of early computer systems \cite{anderson_2018}. As computer systems advanced, particularly with the advent of more sophisticated memory technologies, the role of firmware expanded significantly. Modern memory modules operate at much higher speeds and capacities than their predecessors, requiring precise configuration to ensure stability and optimal performance. Firmware now plays a critical role in managing the memory controller, which is responsible for regulating data flow between the processor and memory modules. This includes configuring memory frequencies, voltage levels, and timing parameters to match the specifications of the installed memory \cite{uefi_spec}\cite{BKDG}. Beyond memory management, firmware responsibilities have broadened to encompass a wide range of system-critical tasks. One key area is power management, where firmware is responsible for optimizing energy consumption across various components of the system. Efficient power management is essential not only for extending battery life in portable devices but also for reducing thermal output and ensuring system longevity in desktop and server environments. Moreover, modern firmware takes on significant roles in hardware initialization and configuration, which were traditionally handled by the operating system. For example, the initialization of USB controllers, network interfaces, and storage devices is now often managed by the firmware during the early stages of the boot process. This shift ensures that the operating system can seamlessly interact with hardware from the moment it takes control, reducing boot times and improving overall system reliability \cite{uefi_spec}. Security has also become a paramount concern for modern firmware. UEFI (Unified Extensible Firmware Interface), which has largely replaced traditional BIOS in modern systems, includes features which prevents unauthorized or malicious software from loading during the boot process. This helps protect the system from rootkits and other low-level malware that could compromise the integrity of the operating system before it even starts \cite{uefi_spec}. In the context of performance tuning, firmware sometimes also plays a key role in enabling and managing overclocking, particularly for the memory subsystem. By allowing adjustments to memory frequencies, voltages, and timings, firmware provides tools for enthusiasts to push their systems beyond default limits. At the same time, it includes safeguards to manage the risks of instability and hardware damage, balancing performance gains with system reliability \cite{anderson_2018}. \\ In summary, the evolution of firmware from simple hardware initialization routines to complex management systems reflects the increasing sophistication of modern computer architectures. Firmware is now a critical layer that not only ensures the correct functioning of hardware components but also optimizes performance, manages power consumption, and enhances system security, making it an indispensable part of contemporary computing. \\ This document will focus on \textit{coreboot} during the next parts to study how modern firmware interact with hardware and also as a basis for improvements. \chapter{Characteristics of ASUS KGPE-D16 mainboard} \begin{figure}[H] \centering \includegraphics[width=0.9\textwidth]{images/kgpe-d16.png} \caption{The KGPE-D16 (CC BY-SA 4.0, 2021)} \end{figure} \newpage \section{Overview of ASUS KGPE-D16 hardware} The ASUS KGPE-D16 server mainboard is a dual-socket motherboard designed to support AMD Family 10h/15h series processors. Released in 2009, this mainboard was later awarded the \textit{Respects Your Freedom} (RYF) certification in March 2017, underscoring its commitment to fully free software compatibility \cite{fsf_ryf}. Indeed, this mainboard can be operated with a fully free firmware such as GNU Boot \cite{gnuboot_status}. \\ This mainboard is equipped with robust hardware components designed to meet the demands of high-performance computing. It features 16 DDR3 DIMM slots, capable of supporting up to 256GB of memory, although certain configurations may be limited to 192GB, with some reports suggesting the potential to support 256GB under specific conditions. In terms of expandability, the KGPE-D16 includes multiple PCIe slots, with five physical slots available, although only four can be used simultaneously due to slot sharing. For storage, the mainboard provides several SATA ports. Networking capabilities are enhanced by integrated dual gigabit Ethernet ports, which provide high-speed connectivity essential for data-intensive tasks and network communication \cite{asus_kgpe_d16_manual}. Additionally, the board is equipped with various peripheral interfaces, including USB ports, audio outputs, and other I/O ports, ensuring compatibility with a wide range of external devices. \\ \begin{figure}[H] \centering \includegraphics[width=0.8\textwidth]{images/fig1_schema_basique.png} \caption{Basic schematics of the ASUS KGPE-D16 Mainboard, ASUS (2011)} \label{fig:d16_basic_schematics} \end{figure} The physical layout of the ASUS KGPE-D16 is meticulously designed to optimize airflow, cooling, and power distribution. All of this is critical for maintaining system stability, particularly under heavy computational loads, as this board was designed for server operations. In particular, key components such as the CPU sockets, memory slots, and PCIe slots are strategically positioned. \\ \begin{figure}[H] \centering \includegraphics[width=0.8\textwidth]{images/kgpe-d16_real.png} \caption{The KGPE-D16, viewed from the top (CC BY-SA 4.0, 2024)} \label{fig:d16_top_view} \end{figure} \section{Chipset} Before diving into the specific components, it is essential to understand the roles of the northbridge and southbridge in traditional motherboard architecture. These chipsets historically managed communication between the CPU and other critical components of the system \cite{amd_chipsets}. \\ The northbridge is a chipset on the motherboard that traditionally manages high-speed communication between the CPU, memory (RAM), and graphics card (if applicable). It serves as a hub for data that needs to move quickly between these components. On the ASUS KGPE-D16, the functions typically associated with the northbridge are divided between the CPU’s internal northbridge and an external SR5690 northbridge chip. The SR5690 specifically acts as a translator and switch, handling the HyperTransport interface, a high-speed communication protocol used by AMD processors, and converting it to ALink and PCIe interfaces, which are crucial for connecting peripherals like graphics cards \cite{SR5690BDG}. Additionally, the northbridge on the KGPE-D16 incorporates the IOMMU (Input-Output Memory Management Unit), which is crucial for ensuring secure and efficient memory access by I/O devices. The IOMMU allows for the virtualization of memory addresses, providing device isolation and preventing unauthorized memory access, which is particularly important in environments that run multiple virtual machines \cite{amd_chipsets}\cite{northbridge_wiki}. \\ The southbridge, on the other hand, is responsible for handling lower-speed, peripheral interfaces such as the PCI, USB, and IDE/SATA connections, as well as managing onboard audio and network controllers. On the KGPE-D16, these functions are managed by the SP5100 southbridge chip, which integrates several critical functions including the LPC bridge, SATA controllers, and other essential I/O operations \cite{amd_chipsets}\cite{southbridge_wiki}. It is essentially an ALink bus controller and includes the hardware interrupt controller, the IOAPIC. Interrupts from peripheral always pass through the northbridge (fig. \ref{fig:d16_ioapic}), since it translates ALink to HyperTransport for the CPUs and contains the IOMMU \cite{SR5690BDG}. \\ \begin{figure}[H] \centering \includegraphics[width=0.9\textwidth]{images/ioapic.png} \caption{Functional diagram presenting the IOAPIC function of the SP5100, ASUS (2011)} \label{fig:d16_ioapic} \end{figure} In addition to the northbridge and southbridge, the KGPE-D16 also contains specialized chips for managing input/output operations and system health monitoring. The WINBOND W83667HG-A Super I/O chip handles traditional I/O functions such as legacy serial and parallel ports, keyboard, and mouse interfaces, but also the SPI chip that contains the firmware \cite{winbond}. Meanwhile, the Nuvoton W83795G/ADG Hardware Monitor oversees the system’s health by monitoring temperatures, voltages, and fan speeds, ensuring that the system operates within safe parameters \cite{nuvoton}. On the KGPE-D16, access to the Super I/O from a CPU core is done through the SR5690, then the SP5100, as that can be observed on the functional diagram of the chipset (fig. \ref{fig:d16_chipset}) \cite{SR5690BDG}. \begin{figure}[H] \centering \includegraphics[width=0.8\textwidth]{images/fig2_diagramme_chipset.png} \caption{Functional diagram of the KGPE-D16 chipset (CC BY-SA 4.0, 2024)} \label{fig:d16_chipset} \end{figure} \section{Processors} The ASUS KGPE-D16 supports AMD Family 10h processors, but it is important to note that Vikings, a known vendor for libre-software-compatible hardware, does not recommend using the Opteron 6100 series due to the lack of IOMMU support, which is critical for security. Fortunately, AMD Family 15h processors are also supported. However, the Opteron 6300 series, while supported, requires proprietary microcode updates for stability, IOMMU functionality, and fixes for specific vulnerabilities, including a gain-root- via-NMI exploit. The Opteron 6200 series does not suffer from these problems and works properly without any proprietary microcode update needed \cite{vikings}. \\ \begin{figure}[H] \centering \includegraphics[width=0.9\textwidth]{images/opteron6200_annoté.png} \caption{Annotated photography of an Opteron 6200 series CPU (2024), from a photography by AMD Inc. (2008)} \label{fig:opteron2600} \end{figure} The Opteron 6200 series, part of the Bulldozer microarchitecture, was designed to target high-performance server applications. These processors feature 16 cores, organized into 8 Bulldozer modules, with each module containing two integer cores that shared resources like the floating-point unit (FPU) and L2 cache (fig. \ref{fig:opteron2600}, \ref{fig:opteron2600_diagram}) \cite{amd_6200}\cite{anandtech_bulldozer}. The architecture of the Opteron 6200 series is built around AMD's Bulldozer core design, which uses Clustered Multithreading (CMT) to maximize resource utilization. This is a technique where each processor module contains two integer cores that share certain resources like the floating-point unit (FPU), L2 cache, and instruction fetch/decode stages. Unlike traditional multithreading, where each core handles multiple threads, CMT allows two cores to share resources to improve parallel processing efficiency. This approach aims to balance performance and resource usage, particularly in multi- threaded workloads, though it can lead to some performance trade-offs in single-threaded tasks. In the Opteron 6272, the processor consists of eight modules, effectively creating 16 integer cores. Due to the CMT architecture, each Opteron 6272 chip functions as two CPUs within a single processor, each with its own set of cores, L2 caches, and shared L3 cache. Here, one CPU is made by four modules, each module in it sharing certain components, such as the FPU and L2 cache, between two integer cores. The L3 cache is shared across these modules. HyperTransport links provide high-speed communication between the two sockets of the KGPE-D16. Shared L3 cache and direct memory access are provided by each socket \cite{amd_6200}\cite{hill_impact_caching}. \\ This architecture also integrates a quad-channel DDR3 memory controller directly into the processor die, which facilitates high bandwidth and low latency access to memory. This memory controller supports DDR3 memory speeds up to 1600 MHz and connects directly to the memory modules via the memory bus. By integrating the memory controller into the processor, the Opteron 6200 series reduces memory access latency, enhancing overall performance \cite{amd_6200}\cite{amd_ddr3_guide}. It is interesting to note that Opterons incorporate the internal northbridge that we cited previously. The traditional northbridge functions, such as memory controller and PCIe interface management, are partially integrated into the processor. This integration reduces the distance data must travel between the CPU and memory, decreasing latency and improving performance, particularly in memory-intensive applications \cite{amd_6200}. \\ \begin{figure}[H] \centering \includegraphics[width=0.8\textwidth]{ images/fig3_img_dual_processor_node.png} \caption{Functional diagram of an Opteron 6200 package (CC BY-SA 4.0, 2024)} \label{fig:opteron2600_diagram} \end{figure} Power efficiency was a key focus in the design of the Opteron 6200 series. Despite the high core count, the processor includes several power management features, such as Dynamic Power Management (DPM) and Turbo Core technology. These features allow the processor to adjust power usage based on workload demands, balancing performance with energy consumption. However, the Bulldozer architecture's focus on high clock speeds and multi-threaded performance resulted in higher power consumption compared to competing architectures \cite{anandtech_bulldozer}. A special model of the series, called \textit{high efficiency} models, solve a bit this problem by proposing a bit less performant processor but with a power consumption divided by a factor from 1.5 to 2.0 in some cases. \\ The processor connected to the I/O hub is known as the Bootstrap Processor (BSP). The BSP is responsible for starting up the system by executing the initial firmware code from the reset vector, a specific memory address where the CPU begins execution after a reset \cite{amd_bsp}. Core 0 of the BSP, called the Bootstrap Core (BSC), initiates this process. During early initialization, the BSP performs several critical tasks, such as memory initialization, and bringing other CPU cores online. One of its duties is storing Built-In Self-Test (BIST) information, which involves checking the integrity of the processor's internal components to ensure they are functioning correctly. The BSP also determines the type of reset that has occurred—whether it's a cold reset, which happens when the system is powered on from an off state, or a warm reset, which is a restart without turning off the power. Identifying the reset type is crucial for deciding which initialization procedures need to be executed \cite{amd_bsp}\cite{BKDG}. \section{Baseboard Management Controller} The Baseboard Management Controller (BMC) on the KGPE-D16 motherboard, specifically the ASpeed AST2050, plays a role in the server's architecture by managing out-of-band communication and control of the hardware. The AST2050 is based on an ARM926EJ-S processor, a low-power 32-bit ARM architecture designed for embedded systems \cite{ast2050_architecture}. This architecture is well-suited for BMCs due to its efficiency and capability to handle multiple management tasks concurrently without significant resource demands from the main system. \\ The AST2050 features several key components that contribute to its functionality. It includes an integrated VGA controller, which enables remote graphical management through KVM-over-IP (Keyboard, Video, Mouse), a critical feature for administrators who need to interact with the system remotely, including BIOS updates and troubleshooting \cite{ast2050_kvm}. Additionally, the AST2050 integrates a dedicated memory controller, which supports up to 256MB of DDR2 RAM. This allows it to handle complex tasks and maintain responsiveness during management operations \cite{ast2050_memory}. The BMC also features a network interface controller (NIC) dedicated to management traffic, ensuring that remote management does not interfere with the primary network traffic of the server. This separation is vital for maintaining secure and uninterrupted system management, especially in environments where uptime is critical \cite{ast2050_nic}. Another important architectural aspect of the AST2050 is its support for multiple I/O interfaces, including I2C, GPIO, UART, and USB, which allow it to interface with various sensors and peripherals on the motherboard \cite{ast2050_io}. This versatility enables comprehensive monitoring of hardware health, such as temperature sensors, fan speeds, and power supplies, all of which can be managed and configured through the BMC. \\ When combined with OpenBMC \cite{openbmc_wiki}, a libre firmware that can be run on the AST2050 thanks to Raptor Engineering \cite{raptor_engineering}, the architecture of the BMC becomes even more powerful. OpenBMC takes advantage of the AST2050's architecture, providing a flexible and customizable environment that can be tailored to specific use cases. This includes adding or modifying features related to security, logging, and network management, all within the BMC's ARM architecture framework \cite{openbmc_customization}. \chapter{Key components in modern firmware} \section{General structure of coreboot} The firmware of the ASUS KGPE-D16 is crucial in ensuring the proper functioning and optimization of the mainboard's hardware components. For this to be done efficiently, \textit{coreboot} is organized in different stages (fig. \ref{fig:coreboot_stages}) \cite{coreboot_docs}. \begin{figure}[H] \centering \includegraphics[width=0.9\textwidth]{ images/fig9_coreboot_stages.png} \caption{\textit{coreboot}'s stages timeline, by \textit{coreboot} project (CC BY-SA 4.0, 2009)} \label{fig:coreboot_stages} \end{figure} Being a complex project with ambitious goals, \textit{coreboot} decided early on to establish an file-system-based architecture for its images (also called ROMs). This special file-system is CBFS (which stands for coreboot file system). The CBFS architecture consists of a binary image that can be interpreted as a physical disk, referred to here as ROM. A number of independent components, each with a header added to the data, are located within the ROM. The components are nominally arranged sequentially, although they are aligned along a predefined boundary (fig. \ref{fig:coreboot_diagram}). \\ Each stage is compiled as a separate binary and inserted into the CBFS with custom compression. The bootblock stage is usually not compressed, while the ramstage and the payload are compressed with LZMA. Each stage loads the next stage at a given address (possibly decompressing it in the process). \\ Some stages are relocatable and can be placed anywhere in the RAM. These stages are typically cached in the CBMEM for faster loading times during wake-up. The CBMEM is a specific memory area used by the \textit{coreboot} firmware to store important data structures and logs during the boot process. This area is typically allocated in the system's RAM and is used to store various types of runtime information that it might need to reference after the initial boot stages. \\ In general, \textit{coreboot} manages main memory through a structured memory map (fig. \ref{tab:memmap}), allocating specific address ranges for various hardware functions and system operations. The first 640KB of memory space is typically unused by coreboot due to historical reasons. Graphics-related operations use the VGA address range and the text mode address ranges. It also reserves the higher for operating system use, ensuring that critical system components like the IOAPIC and TPM registers have dedicated address spaces. This structured approach helps maintain system stability and compatibility across different platforms and allows for a reset vector fixed at an address (\textit{0xFFFFFFF0}), regardless of the ROM size. Payloads are typically loaded into high memory, above the reserved areas for hardware components and system resources. The exact memory location can vary depending on the system's configuration, but generally, payloads are placed in a region of memory that does not conflict with the firmware code or the reserved memory map areas, such as the ROM mapping ranges. This placement ensures that payloads have sufficient space to execute without interfering with other critical memory regions allocated \cite{coreboot_mem_management}. \begin{table}[ht] \makebox[\textwidth][c]{% \begin{tabular}{ |>{\centering\arraybackslash}p{0.35\textwidth} |>{\centering\arraybackslash}p{0.5\textwidth}|} \hline \texttt{0x00000 - 0x9FFFF} & Low memory (first 640KB). Never used. \\ \hline \texttt{0xA0000 - 0xAFFFF} & VGA graphics address range. \\ \hline \texttt{0xB0000 - 0xB7FFF} & Monochrome text mode address range. Few motherboards use it, but the KGPE-D16 does. \\ \hline \texttt{0xB8000 - 0xBFFFF} & Text mode address range. \\ \hline \texttt{0xFEC00000} & IOAPIC address. \\ \hline \texttt{0xFED44000 - 0xFED4FFFF} & Address range for TPM registers. \\ \hline \texttt{0xFF000000 - 0xFFFFFFFF} & 16 MB ROM mapping address range. \\ \hline \texttt{0xFF800000 - 0xFFFFFFFF} & 8 MB ROM mapping address range. \\ \hline \texttt{0xFFC00000 - 0xFFFFFFFF} & 4 MB ROM mapping address range. \\ \hline \texttt{0xFEC00000 - DEVICE MEM HIGH} & Reserved area for OS use. \\ \hline \end{tabular}} \caption{\textit{coreboot} memory map} \label{tab:memmap} \end{table} \subsection{Bootblock stage} The bootblock is the first stage executed after the CPU reset. The beginning of this stage is written in assembly language, and its main task is to set everything up for a C environment. The rest, of course, is written in C. This stage occupies the last 20k (fig. \ref{fig:coreboot_diagram}) of the image and within it is a main header containing information about the ROM, including the size, component alignment, and the offset of the start of the first CBFS component. This block is a mandatory component as it also contains the entry point of the firmware. \\ \begin{figure}[H] \centering \includegraphics[width=0.8\textwidth]{images/fig8_coreboot_architecture.png} \caption{\textit{coreboot} ROM architecture (CC BY-SA 4.0, 2024)} \label{fig:coreboot_diagram} \end{figure} Upon startup, the first responsibility of the bootblock is to execute the code from the reset vector located at the conventional reset vector in 16-bit real mode. This code is specific to the processor architecture and, for our board, is stored in the architecture-specific sources for x86 within \textit{coreboot}. The entry point into \textit{coreboot} code is defined in two files in the \path{src/cpu/x86/16bit/} directory: \texttt{reset16.inc} and \texttt{entry16.inc}. The first file serves as a jump to the \texttt{\_start16bit} procedure defined in the second. Due to space constraints this function must remain below the 1MB address space because the IOMMU has not yet been configured to allow anything else. \\ During this early initialization, the Bootstrap Core (BSC) performs several critical tasks while the other cores remain dormant. These tasks include saving the results (and displaying them if necessary) of the Built-in Self-Test (BIST), formerly known as POST; invalidating the TLB to prevent any address translation errors; determining the type of reset (e.g., cold start or warm start); creating and loading an empty Interrupt Descriptor Table (IDT) to prevent the use of "legacy" interrupts from real mode until protected mode is reached. In practice, this means that at the slightest exception, the BSC will halt. The code then switches to 32-bit protected mode by mapping the first 4 GB of address space for code and data, and finally jumps to the 32-bit reset code labeled \texttt{\_protected\_start}. \\ Once in protected mode, which constitutes the "normal" operating mode for the processor, the next step is to set up the execution environment. To achieve this, the code contained in \path{src/cpu/x86/32bit/entry32.inc}, followed by \path{src/cpu/x86/64bit/entry64.inc}, and finally \path{src/arch/x86/bootblock_crt0.S}, establishes a temporary stack, transitions to long mode (64-bit addressing) with paging enabled, and sets up a proper exception vector table. The execution then jumps to chipset-specific code via the \texttt{bootblock\_pre\_c\_entry} procedure. Once these steps are completed, the bootblock has a minimal C environment. The procedure now involves allocating memory for the BSS, and decompressing and loading the next stage. \\ The jump to \texttt{\_bootblock\_pre\_entry} leads to the code files \path{src/soc/amd/common/block/cpu/car/cache_as_ram.S} and \path{src/vendorcode/amd/agesa/f15tn/gcccar.inc}, which are specific to AMD chipsets. It's worth noting that these files were developed by AMD's engineers as part of the \textit{AGESA} project. The operations performed at this stage are related to pre-RAM memory initialization. All cores of all processors (up to a limit of 64 cores) are started. The \textit{Cache-As-Ram} is configured using the Memory-type range registers. These registers allow the specification of a specific configuration for a given memory area \cite{BKDG}. In this case, the area that should correspond to physical memory is mapped to the cache, while other areas, such as PCI or other bus zones, are configured accordingly. A specific stack is set up for each core of each processor (within the arbitrary limit of 64 cores and 7 nodes, meaning 7 Core 0s). Core 0s receive 16KB, while the Bootstrap Core (BSC) gets 64KB. The other cores receive 4KB each. All cores except the BSC are halted and will restart during the romstage. Finally, the execution jumps to the entry point of the \textit{bootblock} written in C, labeled \texttt{bootblock\_c\_entry}. This entry point is located in \path{src/soc/amd/stoneyridge/bootblock/bootblock.c} and is specific to AMD processors. It is the first C routine executed, and its role is to verify that the current processor is indeed the BSC, allowing the function \path{bootblock_main_with_basetime} to be called exclusively by the BSC. \\ We are now in the file \path{src/lib/bootblock.c}, written by Google's team, and entering the \texttt{bootblock\_main\_with\_basetime} function, which immediately calls \texttt{bootblock\_main\_with\_timestamp}. At this stage, the goal is to start the romstage, but a few more tasks need to be completed. The \texttt{bootblock\_soc\_early\_init} function is called to initialize the I2C bus of the southbridge. The \texttt{bootblock\_fch\_early\_init} function is invoked to initialize the SPI buses (including the one for the ROM) and the serial and "legacy" buses of the southbridge. The CMOS clock is then initialized, followed by the pre-initialization of the serial console. The code then calls the \texttt{bootblock\_mainboard\_init} function, which enters, for the first time, the files specific to the ASUS KGPE-D16 motherboard: \path{src/mainboard/ASUS/kgpe-d16/bootblock.c}. This code performs the northbridge initialization via the \texttt{bootblock\_northbridge\_init} function found in \path{src/northbridge/amd/amdfam10/bootblock.c}. This involves locating the HyperTransport bus and enabling the discovery of devices connected to it (e.g., processors). The southbridge is initialized using the \texttt{bootblock\_southbridge\_init} function from \path{src/southbridge/amd/sb700/bootblock.c}. This function, largely programmed by Timothy Pearson from Raptor Engineering, who performed the first coreboot port for the ASUS KGPE-D16, finalizes the activation of the SPI bus and the connection to the ROM memory via SuperIO. The state of a recovery jumper is then checked (this jumper is intended to reset the CMOS content, although it is not fully functional at the moment, as indicated by the \texttt{FIXME} comment in the code). Control then returns to \texttt{bootblock\_main} in \path{src/lib/bootblock.c}. \\ At this point, everything is ready to enter the romstage. \textit{coreboot} has successfully started and can now continue its execution by calling the \texttt{run\_romstage} function from \path{src/lib/prog_loaders.c}. This function begins by locating the corresponding segment in the ROM via the southbridge and SPI bus using \texttt{prog\_locate}, which utilizes the SPI driver in \path{src/drivers/cbfs_spi.c}. The contents of the romstage are then copied into the cache-as-ram by \texttt{cbfs\_prog\_stage\_load}. Finally, the \texttt{prog\_run} function transitions to the romstage after switching back to 32-bit mode. \subsection{Romstage} The \textit{romstage} in \textit{coreboot} serves the critical function of early initialization of peripherals, particularly system memory. This stage is crucial for setting up the necessary components for the platform's operation, ensuring that everything is in place for subsequent stages of the boot process. During this phase, \textit{coreboot} configures the Advanced Programmable Interrupt Controller (APIC), which is responsible for correctly handling interrupts across multiple CPUs, especially in systems using Symmetric Multiprocessing (SMP). This includes setting up the Local APIC on each processor and the IOAPIC, part of the southbridge, to ensure that interrupts from peripherals are routed to the appropriate CPUs. Additionally, the firmware configures the HyperTransport (HT) technology, a high-speed communication protocol that facilitates data exchange between the processor and the northbridge, ensuring smooth data flow between these components. \\ The \textit{romstage} begins with a call to the \texttt{\_start} function, defined in \path{src/cpu/x86/32bit/entry32.inc} via \path{src/arch/x86/assembly_entry.S}. We then enter the \texttt{cache\_as\_ram\_setup} procedure, written in assembly language, located in \path{src/cpu/amd/car/cache_as_ram.inc}. This procedure configures the cache to load the future \textit{ramstage} and initialize memory based on the number of processors and cores present. Once this is completed, the code calls \texttt{cache\_as\_ram\_main} in \path{src/mainboard/asus/kgpe-d16/romstage.c}, which serves as the main function of the \textit{romstage}. In the \texttt{cache\_as\_ram\_main} function, after reducing the speed of the HyperTransport bus, only the Bootstrap Core (BSC) initializes the spinlocks for the serial console, the CMOS storage memory (used for saving parameters), and the ROM. At this point, the HyperTransport bus is enumerated, and the PCI bridges are temporarily disabled. The port 0x80 of the southbridge, used for motherboard debugging with \textit{Post Codes}, is also initialized. These codes indicate the status of the boot process and can be displayed using special PCI cards connected to the system. The SuperIO is then initialized to activate the serial port, allowing the serial console to follow \textit{coreboot}’s progress in real-time. If everything proceeds as expected, the code 0x30 is sent, and the boot process continues. \\ If the result of the Built-in Self-Test (BIST), saved during the \textit{bootblock}, shows no anomalies, all cores of all nodes are configured, and they are placed back into sleep mode (except for the Core 0s). If everything goes well, the code 0x32 is sent, and the process continues. Using the \texttt{enable\_sr5650\_dev8} function, the southbridge’s P2P bridge is activated. Additionally, a check is performed to ensure that the number of physical processors detected does not exceed the number of sockets available on the board. If any issues were detected during the BIST, the machine will halt, and the error will be displayed on the console. Otherwise, the process continues, and the default hardware information table is constructed, and the microcode of the physical processors is updated if necessary. If everything proceeds correctly, the code 0x33 and then 0x34 is sent, and the process continues. The information about the physical processors is retrieved using \texttt{amd\_ht\_init}, and communication between the two sockets is configured via \texttt{amd\_ht\_fixup}. This process includes disabling any defective HT links (one per socket in this AMD Family 15h chipset). If everything is working as expected, the code 0x35 is sent, and the boot process continues. With the \texttt{finalize\_node\_setup} function, the PCI bus is initialized, and a mapping is created (\texttt{setup\_mb\_resource\_map}). If all goes well, the code 0x36 is sent. This is done in parallel across all Core 0s, so the system waits for all cores to finish using the \texttt{wait\_all\_core0\_started} function. The communication between the northbridge and southbridge is prepared using \texttt{sr5650\_early\_setup} and \texttt{sb7xx\_51xx\_early\_setup}, followed by the activation of all cores on all nodes, with the system waiting for all cores to be fully initialized. If everything is successful, the code 0x38 is sent. \\ At this point, the timer is activated, and a warm reset is performed via the \texttt{soft\_reset} function to validate all configuration changes to the HT, PCI buses, and voltage/power settings of the processors and buses. This results in a system reboot, passing again through the \textit{bootblock}, but much faster this time since the system recognizes the warm reset condition. Once this reboot is complete, the HyperTransport bus is reconfigured into isochronous mode (switching from asynchronous mode), finalizing the configuration process. \\ Memory training and optimization are also key functions of the firmware during the \textit{romstage}. This process involves adjusting memory settings, such as timings, frequencies, and voltages, to ensure that the installed memory modules operate efficiently and stably. This step is crucial for achieving optimal performance, especially when dealing with large amounts of RAM and many CPU cores, as supported by the KGPE-D16. We'll see that in detail during the next chapter. \\ After memory initialization, the process returns to the \texttt{cache\_as\_ram\_main} function, where a memory test is performed. This involves writing predefined values to specific memory locations and then verifying that the values can be read back correctly. If everything passes successfully, the CBMEM is initialized and one sends code \texttt{0x41}. At this point, the configuration of the PCI bus is prepared, which will be completed during the ramstage by configuring the PCI bridges. The system then exits \texttt{cache\_as\_ram\_main} and returns to \texttt{cache\_as\_ram\_setup} to finalize the process. \texttt{coreboot} then transitions to the next stage, known as the postcar stage, where it exits the cache-as-RAM mode and begins using physical RAM. \subsection{Ramstage} The ramstage performs the general initialization of all peripherals, including the initialization of PCI devices, on-chip devices, the TPM (if not done by verstage), graphics (optional), and the CPU (setting up the System Management Mode). After this initialization, tables are written to inform the payload or operating system about the existence and current state of the hardware. These tables include ACPI tables (specific to x86), SMBIOS tables (specific to x86), coreboot tables, and updates to the device tree (specific to ARM). Additionally, the ramstage locks down the hardware and firmware by applying write protection to boot media, locking security-related registers, and locking SMM (specific to x86) \cite{coreboot_docs}. Effective resource allocation is essential for system stability, particularly in complex configurations involving multiple CPUs and peripherals. This stage manages initial resource allocation, resolving any conflicts between hardware components to prevent resource contention and ensure smooth operation and security, which is a major concern in modern systems. This includes support for IOMMU, which is crucial for preventing unauthorized direct memory access (DMA) attacks, particularly in virtualized environments (however there are still vulnerabilities that can be exploited, such as sub-page or IOTLB-based attacks or even configuration weaknesses \cite{medeiros2017}\cite{markuze2021}). \\ \subsubsection{Advanced Configuration and Power Interface} The Advanced Configuration and Power Interface (ACPI) is a critical component of modern computing systems, providing an open standard for device configuration and power management by the operating system (OS). Developed in 1996 by Intel, Microsoft, and Toshiba, ACPI replaced the older Advanced Power Management (APM) standard with more advanced and flexible power management capabilities \cite{intel_acpi_spec}. At its core, ACPI is implemented through a series of data structures and executable code known as ACPI tables, which are provided by the system firmware and interpreted by the OS. These tables describe various aspects of the system, including hardware resources, device power states, and thermal zones. The ACPI Specification outlines these structures and provides the necessary standardization for interoperability across different platforms and operating systems \cite{acpi_os_support}. These tables are used by the OS to perform low-level task, including managing power states of the CPU, controlling the voltage and frequency scaling (also known as Dynamic Voltage and Frequency Scaling, or DVFS), and coordinating power delivery to peripherals. \\ The ACPI Component Architecture (ACPICA) is the reference implementation of ACPI, providing a common codebase that can be used by OS developers to integrate ACPI support. ACPICA includes tools and libraries that allow for the parsing and execution of ACPI Machine Language (AML) code, which is embedded within the ACPI tables \cite{acpi_programming}. One of the key tools in ACPICA is the Intel ACPI Source Language (IASL) compiler, which converts ACPI Source Language (ASL) code into AML bytecode, allowing firmware developers to write custom ACPI methods \cite{intel_acpi_spec}. The triggering of ACPI events is managed through a combination of hardware signals and software routines. For example, when a user presses the power button on a system, an ACPI event is generated, which is then handled by the OS. This event might trigger the system to enter a low-power state, such as sleep or hibernation, depending on the configuration provided by the ACPI tables \cite{acpi_os_support}. These power states are defined in the ACPI specification, with global states (G0 to G3) representing different levels of system power consumption, and device states (D0 to D3) representing individual device power levels. \\ The ASUS KGPE-D16 mainboard, which is designed for server and high-performance computing environments, needs ACPI for managing its power distribution across multiple CPUs and attached peripherals. ACPI is integral in controlling the power states of various components, thereby optimizing performance and energy use. Additionally, the firmware on the KGPE-D16 uses ACPI tables to manage system temperature and fan speed, ensuring reliable operation under heavy workloads \cite{asus_kgpe_d16_manual}. \subsubsection{System Management Mode} System Management Mode (SMM) is a highly privileged operating mode provided by x86 processors for handling system-level functions such as power management, hardware control, and other critical tasks that are to be isolated from the OS and applications. Introduced by Intel, SMM operates in an environment separate from the main operating system, offering a controlled space for executing sensitive operations \cite{uefi_smm_security}. \\ SMM is triggered by a System Management Interrupt (SMI), which is a non-maskable interrupt that causes the CPU to save its current state and switch to executing code stored in a protected area of memory called System Management RAM (SMRAM). SMRAM is a specialized memory region that is isolated from the rest of the system, making it inaccessible to the OS and preventing tampering or interference from other software \cite{heasman2007}. Within SMM, the firmware can execute various low-level functions that require direct hardware control or need to be protected from the OS. This includes tasks such as thermal management, where the system monitors CPU temperature and adjusts performance or power levels to prevent overheating, as well as power management routines that enable efficient energy usage by adjusting power states based on system activity \cite{offsec_bios_smm}. One of the critical security features of SMM is its role in managing firmware updates and handling system-level security events. Because SMM operates in a privileged mode that is isolated from the OS, it can apply firmware updates and could respond to security threats without being affected by potentially compromised system software \cite{domas2015}. However, the high privilege level and isolation of SMM also present significant security challenges. If an attacker can compromise SMM, they gain full control over the system, bypassing all security measures implemented by the OS \cite{cyber_smm_hack}. Also, with a proprietary firmware, it means that this code with a very high priviledge level cannot be audited at all, nor even replaced. \\ The ASUS KGPE-D16 mainboard needs SMM to perform critical management tasks that need to be done in parallel from the operating system. For example, SMM is used to monitor and manage system health by responding to thermal events and adjusting power levels to maintain system stability. SMM operates independently of the main operating system, allowing it to perform sensitive tasks securely. \textit{coreboot} supports SMM, but its implementation is typically minimal compared to traditional proprietary firmware. In \textit{coreboot}, SMM initialization involves setting up the System Management Interrupt (SMI) handler and configuring System Management RAM (SMRAM), the memory region where SMM code executes\cite{brown2003linuxbios}. The extent of SMM support in \textit{coreboot} can vary significantly depending on the hardware platform and the specific requirements of the system. \textit{coreboot}'s design philosophy emphasizes a lightweight and fast boot process, delegating more complex management tasks to payloads or the operating system itself \cite{reinauer2008coreboot}. One of the key challenges with implementing SMM in \textit{coreboot} is ensuring that SMI handlers are configured correctly to manage necessary system tasks without compromising security or performance. \textit{coreboot}'s approach to SMM is consistent with its overall goal of providing a streamlined and efficient firmware solution, leaving more intricate functionalities to be handled by subsequent software layers \cite{mohr2012comparative}. \subsection{Payload} The payload is the software that executes after coreboot has completed its initialization tasks. It resides in the CBFS and is predetermined at compile time, with no option to choose it at runtime. The primary role of the payload is to load and hand control over to the operating system. In some cases, the payload itself can be a component of the operating system \cite{coreboot_docs}. Examples of payloads are \textit{GNU GRUB}, \textit{SeaBIOS}, \textit{memtest86+} or even sometimes the \textit{Linux kernel} itself. \\ \textit{TianoCore}, a free implementation of the UEFI (Unified Extensible Firmware Interface) specification is often used as a payload \cite{tianocore_payload}. It provides a UEFI environment after \textit{coreboot} has completed its initial hardware initialization. This allows the system to benefit from the advanced features of UEFI, such as a more flexible boot manager, enhanced features, and support for modern hardware. Indeed, UEFI, and by extension \textit{TianoCore}, includes a driver model that allows hardware manufacturers to provide UEFI-compatible drivers. These drivers can be loaded at boot time, allowing the firmware to support a wide range of modern devices that \textit{coreboot}, with its more minimalistic and custom-tailored approach, might not support out of the box. For example, GOP drivers are responsible for setting up the graphics hardware in UEFI environments. They replace the older VGA BIOS routines used in legacy BIOS systems. With GOP drivers, the system can initialize the GPU and display a graphical interface even before the operating system loads \cite{osdev_gop}. Hardware manufacturers can distribute proprietary UEFI drivers as part of firmware updates, making it straightforward for end-users to install and use them. This is especially useful for specialized hardware that requires specific drivers not included in the free software community. It also gives hardware vendors more control over how their devices are initialized and used, which can be an advantage for vendors but is a freedom and user control limitation. \\ Payloads are then definitely important parts of the firmware. \section{AMD Platform Security Processor and Intel Management Engine} The AMD Platform Security Processor (PSP) and Intel Management Engine (ME) are embedded subsystems within AMD and Intel processors, respectively, that handle a range of security-related tasks independent of the main CPU. These subsystems are fundamental to the security architecture of modern computing platforms, providing functions such as secure boot, cryptographic key management, and remote system management \cite{amd_psp_overview}. The AMD PSP is based on an ARM Cortex-A5 processor and is responsible for several security functions, including the validation of firmware during boot (secure boot), management of Trusted Platform Module (TPM) functions, and handling cryptographic operations such as key generation and storage. The PSP operates independently of the main x86 cores, which allows it to execute security functions even when the main system is powered off or compromised by malware \cite{amd_psp_overview}. The PSP's isolated environment ensures that sensitive operations are protected from threats that could affect the main OS. \\ Similarly, the Intel Management Engine (ME) is a dedicated processor embedded within Intel chipsets that operates independently of the main CPU. The ME is a comprehensive subsystem that provides a variety of functions, including out-of-band system management, security enforcement, and support for Digital Rights Management (DRM) \cite{intel_csme}. The ME's firmware runs on an isolated environment that allows it to perform these tasks securely, even when the system is powered off. This capability is crucial for enterprise environments where administrators need to perform remote diagnostics, updates, and security checks without relying on the main OS. Intel ME enforces Digital Rights Management (DRM) through a multifaceted approach leveraging its deeply embedded, hardware-based capabilities. At the core is the Protected Execution Environment (PEE), which operates independently from the main CPU and operating system. This isolation allows to privately manage cryptographic keys, certificates, and other sensitive data critical for DRM, which can be very problematic from a user freedom perspective \cite{fsf_intel_me}. By handling encryption and decryption processes within this protected environment, Intel ME ensures that DRM-protected content, such as video streams, remains secure and unreachable by the user, raising concerns about the control users have over their own devices \cite{eff_intel_me}. Intel ME also plays a significant role in maintaining platform integrity through the secure boot process. During secure boot, Intel ME ensures that only digitally signed and authorized operating systems and applications are loaded, which can prevent users from installing alternative or modified software on their own hardware, further restricting their freedom \cite{uefi_what_is_uefi}. This is further reinforced by Intel ME's remote attestation capabilities, where the system’s state is reported to a remote server. This process verifies that only systems meeting specific security standards—dictated by third parties—are allowed to access DRM-protected content, potentially limiting users' control over their own devices \cite{proprivacy_intel_me}. Moreover, Intel ME supports High-bandwidth Digital Content Protection (HDCP), a technology that restricts how digital content is transmitted over interfaces like HDMI or DisplayPort. By enforcing HDCP, Intel ME ensures that protected digital content, such as high-definition video, is only transmitted to and displayed on authorized devices, effectively preventing users from freely using the content they have legally acquired \cite{phoronix_hdcp_2_2_i915}\cite{kernel_mei_hdcp}. Together, these features enable Intel ME to provide a comprehensive and robust DRM enforcement mechanism. However, this also means that users have less control over their own hardware and digital content, raising serious concerns about privacy, user autonomy, and the broader implications for freedom in computing \cite{fsf_intel_me}\cite{netgarage_intel_me}. \\ Added to that, Intel ME has been a source of controversy due to its deep integration into the hardware and its potential to be exploited if vulnerabilities are discovered. Researchers have demonstrated ways to hack into the ME, potentially gaining control over a system even when it is powered off \cite{blackhat_me_hack}. These concerns have led to calls for greater transparency and security measures around the ME and similar subsystems. When comparing Intel ME and AMD PSP, the primary difference lies in their scope and functionality. Intel ME offers more extensive remote management capabilities, making it a more comprehensive tool for enterprise environments, while AMD PSP focuses more narrowly on core security tasks. Nonetheless, both play critical roles in ensuring the security and integrity of modern computing systems. \\ The ASUS KGPE-D16 mainboard does not include AMD PSP nor Intel ME. \chapter{Memory initialization and training algorithms [WIP]} \section{Importance of memory initialization} \begin{itemize} \item Steps involved in initializing the memory controller \item Critical role in system stability and performance \item \textbf{ASUS KGPE-D16 Example}: Memory initialization process on the KGPE-D16 mainboard \end{itemize} Memory training involves several steps: 1. **Detection and Initialization**: The BIOS detects the installed memory modules, determining their size, speed, and type. 2. **Configuration and Timing Setup**: The BIOS configures the memory controller settings, including timings for memory access such as CAS latency, RAS to CAS delay, and other parameters\cite{intel_uefi}. 3. **Training and Calibration**: The BIOS performs tests and adjustments to calibrate the memory system, ensuring stable operation at optimal speeds by adjusting signal voltages and testing data integrity\cite{wolf2006}. These steps are crucial for modern systems, where improper memory configuration can lead to instability, data corruption, or suboptimal performance. Memory timings, such as CAS latency, RAS to CAS delay, and others, must be finely tuned to ensure optimal performance. The BIOS uses a combination of predefined profiles and dynamic adjustments to achieve the best balance between speed and stability. Advanced timing optimization involves setting these parameters to ensure that memory operations are performed with minimal latency and maximum throughput\cite{russinovich2012}. \begin{listing}[H] \begin{adjustwidth}{0.5cm}{0.5cm} \inputminted{c}{listings/test.c} \end{adjustwidth} \caption{\textit{Example C code}} \label{lst:c_code} \end{listing} We saw that in (lst. \ref{lst:c_code}). \section{Memory training algorithms} \begin{itemize} \item Techniques used for training memory \item Optimization of timings and voltage settings \item Challenges in multi-core CPU environments \item \textbf{ASUS KGPE-D16 Example}: Specific algorithms used for memory training in the mainboard and their performance outcomes \end{itemize} To optimize memory performance, the BIOS employs various training algorithms and calibration techniques. These methods test the memory under different conditions and make necessary adjustments to improve stability and efficiency. Key techniques include voltage adjustments, data integrity testing, and signal timing calibration\cite{shin2011}. Voltage adjustments involve tweaking the power supplied to the memory modules to ensure reliable operation. Data integrity testing checks that data can be accurately read and written, while signal timing calibration fine-tunes the delays between different memory operations to minimize latency. \section{Practical examples} \begin{itemize} \item Real-world scenarios where firmware played a crucial role in system performance \item Analysis of firmware updates and their impact on the KGPE-D16 mainboard \item User experiences and testimonials highlighting the importance of firmware \item \textbf{ASUS KGPE-D16 Example}: Specific case studies and firmware updates for the mainboard \end{itemize} \subsection{RAM Initialization Preparation} Memory initialization is one of the most critical tasks performed by \texttt{coreboot}. Without proper memory initialization, the system memory cannot function correctly, preventing the operating system from booting. The process begins by setting a default voltage for the memory modules. This is a preliminary step, as the initialization process will subsequently involve searching for an optimal voltage. The function \texttt{set\_peripheral\_control\_lines} is then called to enable various peripherals, such as IEEE1394-compatible devices (e.g., integrated FireWire on the motherboard). Next, the system waits for all cores, except the Bootstrap Processor (BSP), to halt using \texttt{wait\_all\_other\_cores\_stopped}. If everything is in order, the system sends code \texttt{0x38}. \subsection{RAM Initialization} The process starts by calling the \texttt{fill\_mem\_ctrl} function from \texttt{src/northbridge/amd/amdfam10/raminit\_sysinfo\_in\_ram.c}. This function iterates over all memory controllers (one per node) and initializes their corresponding structures with the system information needed for the RAM to function. This includes the addresses of PCI nodes (important for DMA operations) and SPD addresses, which are internal ROMs in each memory slot containing crucial information for detecting and initializing memory modules. If successful, the system posts codes \texttt{0x3D} and then \texttt{0x40}. The \texttt{raminit\_amdmct} function from \texttt{src/northbridge/amd/amdfam10/raminit\_amdmct.c} is then called. This function, in turn, calls \texttt{mctAutoInitMCT\_D} from \texttt{src/northbridge/amd/amdmct/mct\_ddr3/mct\_d.c}, which is responsible for the initial memory initialization, predominantly written by Raptor Engineering. \subsubsection{Memory Controller Initialization} At this stage, it is assumed that memory has been pre-mapped contiguously from address 0 to 4GB and that the previous code has correctly mapped non-cacheable I/O areas below 4GB for the PCI bus and Local APIC access for processor cores. The following prerequisites must be in place from the previous steps: \begin{itemize} \item The HyperTransport bus is configured, and its speed is correctly set. \item The SMBus controller is configured. \item The BSP is in unreal mode. \item A stack is set up for all cores. \item All cores are initialized at a frequency of 2GHz. \item The NVRAM has been verified with checksums. \end{itemize} The memory controller for the BSP is queried to check if it can manage ECC memory, which is a type of memory that includes error-correcting code to detect and correct common types of data corruption. For each node available in the system, the memory controllers are identified and initialized using a \texttt{DCTStatStruc} structure defined in \texttt{src/northbridge/amd/amdmct/mct\_ddr3/mct\_d.h}. This structure contains all necessary fields for managing a memory module. The process includes: \begin{itemize} \item Retrieving the corresponding field in the sysinfo structure for the node. \item Clearing fields with \texttt{zero}. \item Initializing basic fields. \item Initializing the controller linked to the current node. \item Verifying the presence of the node (checking if the processor associated with this controller is present). If yes, the SMBus is informed. \item Pre-initializing the memory module controller for this node using \texttt{mct\_preInitDCT}. \end{itemize} \subsubsection{Memory Module Training} Memory modules are designed to store data. The only valid operations on memory devices are reading data stored in the device, writing (or storing) data to the device, and refreshing the data. Memory modules consist of large rectangular arrays of memory cells, including circuits used to read and write data into the arrays and refresh circuits to maintain data integrity. The memory arrays are organized into rows and columns of memory cells, known as word lines and bit lines, respectively. Each memory cell has a unique location or address defined by the intersection of a row and a column. A DDR3 DIMM module contains 240 contacts. The DDR3 memory interface, used by the Asus KGPE-D16, is source-synchronous. Each memory module generates a Data Strobe (DQS) pulse simultaneously with the data (DQ) it sends during a read operation. Similarly, a DQS is generated with DQ information during a write operation. The DQS differs between write and read operations. For writes, the DQS is centered in the data bit period, whereas for reads, the DQS provided by the memory is aligned with the data period's edge. To improve timing margins or reduce simultaneous switching noise, the DDR3 memory interface allows for adjusting various timing parameters. For systems using dual-inline memory modules (DIMMs), as in this case, the interface provides write leveling: a timing adjustment that compensates for variations in signal travel time. To ensure proper timing margins, the write triggering of the interface must correspond to the command signal's arrival time, which can be resolved by adjusting the DQ and DQS launch times for each device. Each module uses the DQS to sample the clock, asynchronously returning the sampled clock signal to the controller on one or more data lines. To calibrate the write leveling adjustments, the memory controller sweeps the DQS for each data group across its delay range. The \texttt{coreboot} code compensates for the delay between DQS and DQ signals, as well as between CMD and DQ. This is handled in the \texttt{DQSTiming\_D} function. Finally, if the RAM is of the ECC type, error-correcting codes are enabled, and the function ends by activating power-saving features if requested by the user. \chapter{Virtualization of the operating system through firmware abstraction} In contemporary computing systems, the operating system (OS) no longer interacts directly with hardware in the same way it did in earlier computing architectures. Instead, the OS operates within a highly abstracted environment, where critical functions are managed by various firmware components such as ACPI, SMM, UEFI, Intel Management Engine (ME), and AMD Platform Security Processor (PSP). This layered abstraction has led to the argument that the OS is effectively running in a virtualized environment, akin to a virtual machine (VM). \section{ACPI and abstraction of hardware control} The Advanced Configuration and Power Interface (ACPI) provides a standardized method for the OS to manage hardware configuration and power states, effectively abstracting the underlying hardware complexities. ACPI abstracts hardware details, allowing the OS to interact with hardware components without needing direct control over them. This abstraction is similar to how a hypervisor abstracts physical hardware for VMs, enabling a consistent interface regardless of the underlying hardware specifics. \\ According to \textcite{bellosa2010}, the abstraction provided by ACPI not only simplifies the OS's interaction with hardware but also limits the OS's ability to fully control the hardware, which is instead managed by ACPI-compliant firmware. This layer of abstraction contributes to the virtualization-like environment in which the OS operates. \\ \section{SMM as a hidden execution layer} System Management Mode (SMM) is a special-purpose operating mode provided by x86 processors, designed to handle system-wide functions such as power management, thermal monitoring, and hardware control, independent of the OS. SMM operates transparently to the OS, executing code that the OS cannot detect or control, similar to how a hypervisor controls the execution environment of VMs. \\ Research by \textcite{huang2009invisible} argues that SMM introduces a hidden layer of execution that diminishes the OS's control over the hardware, creating a virtualized environment where the OS is unaware of and unable to influence certain system-level operations. This hidden execution layer reinforces the idea that the OS runs in an environment similar to a VM, with the firmware acting as a hypervisor. \\ \section{UEFI and persistence} The Unified Extensible Firmware Interface (UEFI) has largely replaced the traditional BIOS in modern systems, providing a sophisticated environment that includes a kernel-like structure capable of running drivers and applications independently of the OS. UEFI remains active even after the OS has booted, continuing to manage certain hardware functions, which abstracts these functions away from the OS. \\ \textcite{mcclean2017uefi} discusses how UEFI creates a persistent execution environment that overlaps with the OS's operation, effectively placing the OS in a position where it runs on top of another controlling layer, much like a guest OS in a VM. This persistence and the ability of UEFI to manage hardware resources independently further blur the lines between traditional OS operation and virtualized environments. \\ \section{Intel and AMD: control beyond the OS} Intel Management Engine (ME) and AMD Platform Security Processor (PSP) are embedded microcontrollers within Intel and AMD processors, respectively. These components run their own firmware and operate independently of the main CPU, handling tasks such as security enforcement, remote management, and digital rights management (DRM). \\ \textcite{bulygin2013chipset} highlights how these microcontrollers have control over the system that supersedes the OS, managing hardware and security functions without the OS's knowledge or consent. This level of control is reminiscent of a hypervisor that manages the resources and security of VMs. The OS, in this context, operates similarly to a VM that does not have full control over the hardware it ostensibly manages. \\ \section{The OS as a virtualized environment} The combined effect of these firmware components (ACPI, SMM, UEFI, Intel ME, and AMD PSP) creates an environment where the OS operates in a virtualized or highly abstracted layer. The OS does not directly manage the hardware; instead, it interfaces with these firmware components, which themselves control the hardware resources. This situation is analogous to a virtual machine, where the guest OS operates on virtualized hardware managed by a hypervisor. \\ \textcite{smith2019firmware} argues that modern OS environments, influenced by these firmware components, should be considered virtualized environments. The firmware acts as an intermediary layer that abstracts and controls hardware resources, thereby limiting the OS's direct access and control. \\ The presence and operation of modern firmware components such as ACPI, SMM, UEFI, Intel ME, and AMD PSP contribute to a significant abstraction of hardware from the OS. This abstraction creates an environment that parallels the operation of a virtual machine, where the OS functions within a controlled, virtualized layer managed by these firmware systems. The growing body of research supports this perspective, suggesting that the traditional notion of an OS directly managing hardware is increasingly outdated in the face of these complex, autonomous firmware components. \chapter*{Conclusion} \addcontentsline{toc}{chapter}{Conclusion} This document has explored the evolution and current state of firmware, particularly focusing on the transition from traditional BIOS to more advanced firmware interfaces such as UEFI and \textit{coreboot}. The evolution from a simple set of routines stored in ROM to complex systems like UEFI and \textit{coreboot} highlights the growing importance of firmware in modern computing. Firmware now plays a critical role not only in hardware initialization but also in memory management, security, and system performance optimization. \\ The study of the ASUS KGPE-D16 mainboard illustrates how firmware, particularly \textit{coreboot}, plays a crucial role in the efficient and secure operation of high-performance systems. The KGPE-D16, with its support for free software-compatible firmware, exemplifies the potential of libre firmware to deliver both high performance and freedom from proprietary constraints. However, it is important to acknowledge that the KGPE-D16 is not without its imperfections. The detailed analysis of firmware components, such as the bootblock, romstage, and especially the RAM initialization and training algorithms, reveals areas where the firmware can be further refined to enhance system stability and performance. These improvements are not only beneficial for the KGPE-D16 but can also be applied to other boards, extending the impact of these optimizations across a broader range of hardware. \\ Moreover, the discussion on modern firmware components such as ACPI, SMM, UEFI, Intel ME, and AMD PSP demonstrates how these elements abstract hardware from the operating system, creating a virtualized environment where the OS operates more like a guest in a hypervisor-controlled system. This abstraction raises important considerations about control, security, and user freedom in contemporary computing. As we continue to witness the increasing complexity and influence of firmware in computing, it becomes crucial to advocate for free software-compatible hardware. The dependence on proprietary firmware and the associated restrictions on user freedom are growing concerns that need to be addressed. The development and adoption of libre firmware solutions, such as \textit{coreboot} and GNU Boot, are essential steps towards ensuring that users retain control over their hardware and software environments. \\ It is imperative that the community of developers, researchers, and users come together to support and contribute to the development of free firmware. By fostering innovation and collaboration in this field, we can advance towards a future where free software-compatible hardware becomes the norm, ensuring that computing remains open, secure, and under the control of its users. The significance of a libre BIOS cannot be overstated, it is the foundation upon which a truly free and open computing ecosystem can be built \cite{coreboot_fsf}. The importance of the GNU Boot project cannot be overstated. As a fully free firmware initiative, GNU Boot represents a critical step towards achieving truly libre BIOSes, ensuring that users can maintain full control over their hardware and firmware environments. The continued development and support of GNU Boot are essential for advancing the goals of free software and protecting user freedoms in the increasingly complex landscape of modern computing. \\ \newpage % Bibliography \nocite{*} \addcontentsline{toc}{chapter}{Bibliography} \printbibliography \newpage % List of figures \addcontentsline{toc}{chapter}{List of Figures} \listoffigures \newpage % List of figures \addcontentsline{toc}{chapter}{List of Listings} \listoflistings \newpage \chapter*{\center\rlap{GNU Free Documentation License}} \addcontentsline{toc}{chapter}{GNU Free Documentation License} Version 1.3, 3 November 2008 Copyright \copyright{} 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. \bigskip \texttt{} \bigskip Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. \bigskip\bigskip{\bf\large Preamble}\bigskip The purpose of this License is to make a manual, textbook, or other functional and useful document ``free'' in the sense of freedom: to assure everyone the effective freedom to copy and redistribute it, with or without modifying it, either commercially or noncommercially. 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The operator of an MMC Site may republish an MMC contained in the site under CC-BY-SA on the same site at any time before August 1, 2009, provided the MMC is eligible for relicensing. \bigskip\bigskip{\Large\bf ADDENDUM: How to use this License for your documents\par}\bigskip To use this License in a document you have written, include a copy of the License in the document and put the following copyright and license notices just after the title page: \bigskip \begin{quote} Copyright \copyright{} YEAR YOUR NAME. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled ``GNU Free Documentation License''. \end{quote} \bigskip If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts, replace the ``with \dots\ Texts.''\ line with this: \bigskip \begin{quote} with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts being LIST. \end{quote} \bigskip If you have Invariant Sections without Cover Texts, or some other combination of the three, merge those two alternatives to suit the situation. If your document contains nontrivial examples of program code, we recommend releasing these examples in parallel under your choice of free software license, such as the GNU General Public License, to permit their use in free software. \end{document}