114 lines
3.5 KiB
PHP
114 lines
3.5 KiB
PHP
.align 4096
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#endif
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.code16
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.globl _start16bit
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.type _start16bit, @function
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_start16bit:
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cli
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/* Save the BIST result */
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movl %eax, %ebp
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#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
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post_code(POST_RESET_VECTOR_CORRECT)
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#endif
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/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
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* executing any further code. Even though paging is disabled we
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* could still get false address translations due to the TLB if we
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* didn't invalidate it. Thanks to kmliu@sis.com.tw for this TLB fix.
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*/
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB*/
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/* Invalidating the cache here seems to be a bad idea on
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* modern processors. Don't.
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* If we are hyperthreaded or we have multiple cores it is bad,
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* for SMP startup. On Opterons it causes a 5 second delay.
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* Invalidating the cache was pure paranoia in any event.
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* If your CPU needs it you can write a CPU dependent version of
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* entry16.inc.
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*/
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/* Note: gas handles memory addresses in 16 bit code very poorly.
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* In particular it doesn't appear to have a directive allowing you
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* associate a section or even an absolute offset with a segment register.
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*
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* This means that anything except cs:ip relative offsets are
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* a real pain in 16 bit mode. And explains why it is almost
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* impossible to get gas to do lgdt correctly.
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*
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* One way to work around this is to have the linker do the
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* math instead of the assembler. This solves the very
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* pratical problem of being able to write code that can
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* be relocated.
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*
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* An lgdt call before we have memory enabled cannot be
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* position independent, as we cannot execute a call
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* instruction to get our current instruction pointer.
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* So while this code is relocateable it isn't arbitrarily
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* relocatable.
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*
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* The criteria for relocation have been relaxed to their
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* utmost, so that we can use the same code for both
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* our initial entry point and startup of the second CPU.
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* The code assumes when executing at _start16bit that:
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* (((cs & 0xfff) == 0) and (ip == _start16bit & 0xffff))
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* or
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* ((cs == anything) and (ip == 0)).
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*
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* The restrictions in reset16.inc mean that _start16bit initially
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* must be loaded at or above 0xffff0000 or below 0x100000.
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*
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* The linker scripts computes gdtptr16_offset by simply returning
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* the low 16 bits. This means that the initial segment used
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* when start is called must be 64K aligned. This should not
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* restrict the address as the ip address can be anything.
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*
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* Also load an IDT with NULL limit to prevent the 16bit IDT being used
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* in protected mode before c_start.S sets up a 32bit IDT when entering
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* RAM stage. In practise: CPU will shutdown on any exception.
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* See IA32 manual Vol 3A 19.26 Interrupts.
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*/
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movw %cs, %ax
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shlw $4, %ax
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movw $nullidt_offset, %bx
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subw %ax, %bx
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lidt %cs:(%bx)
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movw $gdtptr16_offset, %bx
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subw %ax, %bx
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lgdtl %cs:(%bx)
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* Restore BIST to %eax */
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movl %ebp, %eax
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/* Now that we are in protected mode jump to a 32 bit code segment. */
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ljmpl $ROM_CODE_SEG, $__protected_start
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/**
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* The gdt is defined in entry32.inc, it has a 4 Gb code segment
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* at 0x08, and a 4 GB data segment at 0x10;
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*/
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.align 4
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.globl gdtptr16
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gdtptr16:
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.word gdt_end - gdt -1 /* compute the table limit */
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.long gdt /* we know the offset */
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.align 4
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.globl nullidt
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nullidt:
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.word 0 /* limit */
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.long 0
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.word 0
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.globl _estart16bit
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_estart16bit:
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.code32
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