65 lines
5.9 KiB
TeX
65 lines
5.9 KiB
TeX
\babel@toc {english}{}\relax
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\contentsline {chapter}{Acknowledgments}{3}{chapter*.1}%
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\contentsline {chapter}{Abstract}{4}{chapter*.2}%
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\contentsline {chapter}{List of Figures}{7}{chapter*.2}%
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\contentsline {chapter}{List of Listings}{8}{chapter*.2}%
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\contentsline {chapter}{\numberline {1}Introduction to firmware and BIOS evolution}{10}{chapter.1}%
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\contentsline {section}{\numberline {1.1}Historical context of BIOS}{10}{section.1.1}%
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\contentsline {subsection}{\numberline {1.1.1}Definition and origin}{10}{subsection.1.1.1}%
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\contentsline {subsection}{\numberline {1.1.2}Functionalities and limitations}{11}{subsection.1.1.2}%
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\contentsline {section}{\numberline {1.2}Modern BIOS and UEFI}{12}{section.1.2}%
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\contentsline {subsection}{\numberline {1.2.1}Transition from traditional BIOS to UEFI (Unified Extensible Firmware Interface)}{12}{subsection.1.2.1}%
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\contentsline {subsection}{\numberline {1.2.2}An other way with \textit {coreboot}}{12}{subsection.1.2.2}%
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\contentsline {section}{\numberline {1.3}Shift in firmware responsibilities}{14}{section.1.3}%
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\contentsline {chapter}{\numberline {2}Characteristics of ASUS KGPE-D16 mainboard}{15}{chapter.2}%
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\contentsline {section}{\numberline {2.1}Overview of ASUS KGPE-D16 hardware}{16}{section.2.1}%
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\contentsline {section}{\numberline {2.2}Chipset}{17}{section.2.2}%
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\contentsline {section}{\numberline {2.3}Processors}{19}{section.2.3}%
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\contentsline {section}{\numberline {2.4}Baseboard Management Controller}{20}{section.2.4}%
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\contentsline {chapter}{\numberline {3}Key components in modern firmware}{22}{chapter.3}%
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\contentsline {section}{\numberline {3.1}General structure of coreboot}{22}{section.3.1}%
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\contentsline {subsection}{\numberline {3.1.1}Bootblock}{23}{subsection.3.1.1}%
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\contentsline {subsection}{\numberline {3.1.2}Romstage}{25}{subsection.3.1.2}%
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\contentsline {subsection}{\numberline {3.1.3}Ramstage}{26}{subsection.3.1.3}%
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\contentsline {subsubsection}{\numberline {3.1.3.1}Advanced Configuration and Power Interface}{26}{subsubsection.3.1.3.1}%
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\contentsline {subsubsection}{\numberline {3.1.3.2}System Management Mode}{27}{subsubsection.3.1.3.2}%
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\contentsline {subsection}{\numberline {3.1.4}Payload}{27}{subsection.3.1.4}%
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\contentsline {section}{\numberline {3.2}AMD Platform Security Processor and Intel Management Engine}{28}{section.3.2}%
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\contentsline {chapter}{\numberline {4}Memory initialization and training}{30}{chapter.4}%
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\contentsline {section}{\numberline {4.1}Importance of DDR3 Memory Initialization}{30}{section.4.1}%
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\contentsline {subsection}{\numberline {4.1.1}General steps for DDR3 configuration}{31}{subsection.4.1.1}%
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\contentsline {section}{\numberline {4.2}Memory initialization techniques}{34}{section.4.2}%
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\contentsline {subsection}{\numberline {4.2.1}Memory training algorithms}{34}{subsection.4.2.1}%
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\contentsline {subsection}{\numberline {4.2.2}BIOS and Kernel Developer Guide (BKDG) recommendations}{35}{subsection.4.2.2}%
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\contentsline {subsubsection}{\numberline {4.2.2.1}DDR3 initialization procedure}{36}{subsubsection.4.2.2.1}%
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\contentsline {subsubsection}{\numberline {4.2.2.2}ZQ calibration process}{36}{subsubsection.4.2.2.2}%
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\contentsline {subsubsection}{\numberline {4.2.2.3}Write leveling process}{37}{subsubsection.4.2.2.3}%
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\contentsline {section}{\numberline {4.3}Current implementation and potential improvements}{39}{section.4.3}%
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\contentsline {subsection}{\numberline {4.3.1}Current implementation in coreboot on the KGPE-D16}{39}{subsection.4.3.1}%
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\contentsline {subsubsection}{\numberline {4.3.1.1}Details on the DQS training function}{48}{subsubsection.4.3.1.1}%
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\contentsline {subsubsection}{\numberline {4.3.1.2}Details on the write leveling implementation}{51}{subsubsection.4.3.1.2}%
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\contentsline {subsubsection}{\numberline {4.3.1.3}Details on the write leveling implementation}{54}{subsubsection.4.3.1.3}%
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\contentsline {subsection}{\numberline {4.3.2}Write Leveling on AMD Fam15h G34 Processors with RDIMMs}{54}{subsection.4.3.2}%
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\contentsline {subsubsection}{\numberline {4.3.2.1}Details on the DQS position training function}{55}{subsubsection.4.3.2.1}%
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\contentsline {subsubsection}{\numberline {4.3.2.2}Details on the DQS receiver training function}{57}{subsubsection.4.3.2.2}%
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\contentsline {subsection}{\numberline {4.3.3}Potential enhancements}{60}{subsection.4.3.3}%
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\contentsline {subsubsection}{\numberline {4.3.3.1}DQS receiver training}{60}{subsubsection.4.3.3.1}%
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\contentsline {subsubsection}{\numberline {4.3.3.2}Write leveling}{61}{subsubsection.4.3.3.2}%
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\contentsline {subsection}{\numberline {4.3.4}DQS position training}{63}{subsection.4.3.4}%
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\contentsline {subsection}{\numberline {4.3.5}On a wider scale...}{65}{subsection.4.3.5}%
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\contentsline {subsubsection}{\numberline {4.3.5.1}Saving training values in NVRAM}{65}{subsubsection.4.3.5.1}%
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\contentsline {subsubsection}{\numberline {4.3.5.2}A seedless DQS position training algorithm}{66}{subsubsection.4.3.5.2}%
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\contentsline {chapter}{\numberline {5}Virtualization of the operating system through firmware abstraction}{68}{chapter.5}%
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\contentsline {section}{\numberline {5.1}ACPI and abstraction of hardware control}{68}{section.5.1}%
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\contentsline {section}{\numberline {5.2}SMM as a hidden execution layer}{69}{section.5.2}%
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\contentsline {section}{\numberline {5.3}UEFI and persistence}{69}{section.5.3}%
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\contentsline {subsection}{\numberline {5.3.1}Memory Management}{70}{subsection.5.3.1}%
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\contentsline {subsection}{\numberline {5.3.2}File System Management}{70}{subsection.5.3.2}%
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\contentsline {subsection}{\numberline {5.3.3}Device Drivers}{70}{subsection.5.3.3}%
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\contentsline {subsection}{\numberline {5.3.4}Power Management}{70}{subsection.5.3.4}%
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\contentsline {section}{\numberline {5.4}Intel and AMD: control beyond the OS}{70}{section.5.4}%
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\contentsline {section}{\numberline {5.5}The OS as a virtualized environment}{71}{section.5.5}%
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\contentsline {chapter}{Conclusion}{72}{chapter*.4}%
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\contentsline {chapter}{Bibliography}{73}{chapter*.4}%
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\contentsline {chapter}{GNU Free Documentation License}{80}{chapter*.6}%
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