46 lines
3.9 KiB
TeX
46 lines
3.9 KiB
TeX
\babel@toc {english}{}\relax
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\contentsline {chapter}{Abstract}{5}{chapter*.1}%
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\contentsline {chapter}{\numberline {1}Introduction to firmware and BIOS evolution}{6}{chapter.1}%
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\contentsline {section}{\numberline {1.1}Historical context of BIOS}{6}{section.1.1}%
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\contentsline {subsection}{\numberline {1.1.1}Definition and origin}{6}{subsection.1.1.1}%
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\contentsline {subsection}{\numberline {1.1.2}Functionalities and limitations}{7}{subsection.1.1.2}%
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\contentsline {section}{\numberline {1.2}Modern BIOS and UEFI}{8}{section.1.2}%
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\contentsline {subsection}{\numberline {1.2.1}Transition from traditional BIOS to UEFI (Unified Extensible Firmware Interface)}{8}{subsection.1.2.1}%
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\contentsline {subsection}{\numberline {1.2.2}An other way with \textit {coreboot}}{8}{subsection.1.2.2}%
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\contentsline {section}{\numberline {1.3}Shift in firmware responsibilities}{10}{section.1.3}%
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\contentsline {chapter}{\numberline {2}Characteristics of ASUS KGPE-D16 mainboard}{11}{chapter.2}%
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\contentsline {section}{\numberline {2.1}Overview of ASUS KGPE-D16 hardware}{12}{section.2.1}%
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\contentsline {section}{\numberline {2.2}Chipset}{13}{section.2.2}%
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\contentsline {section}{\numberline {2.3}Processors}{15}{section.2.3}%
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\contentsline {section}{\numberline {2.4}Baseboard Management Controller}{16}{section.2.4}%
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\contentsline {chapter}{\numberline {3}Key components in modern firmware}{18}{chapter.3}%
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\contentsline {section}{\numberline {3.1}General structure of coreboot}{18}{section.3.1}%
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\contentsline {subsection}{\numberline {3.1.1}Bootblock stage}{19}{subsection.3.1.1}%
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\contentsline {subsection}{\numberline {3.1.2}Romstage}{21}{subsection.3.1.2}%
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\contentsline {subsection}{\numberline {3.1.3}Ramstage}{22}{subsection.3.1.3}%
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\contentsline {subsubsection}{\numberline {3.1.3.1}Advanced Configuration and Power Interface}{22}{subsubsection.3.1.3.1}%
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\contentsline {subsubsection}{\numberline {3.1.3.2}System Management Mode}{23}{subsubsection.3.1.3.2}%
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\contentsline {subsection}{\numberline {3.1.4}Payload}{23}{subsection.3.1.4}%
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\contentsline {section}{\numberline {3.2}AMD Platform Security Processor and Intel Management Engine}{24}{section.3.2}%
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\contentsline {chapter}{\numberline {4}Memory initialization and training algorithms [WIP]}{26}{chapter.4}%
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\contentsline {section}{\numberline {4.1}Importance of memory initialization}{26}{section.4.1}%
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\contentsline {section}{\numberline {4.2}Memory training algorithms}{26}{section.4.2}%
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\contentsline {section}{\numberline {4.3}Practical examples}{27}{section.4.3}%
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\contentsline {subsection}{\numberline {4.3.1}RAM Initialization Preparation}{27}{subsection.4.3.1}%
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\contentsline {subsection}{\numberline {4.3.2}RAM Initialization}{27}{subsection.4.3.2}%
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\contentsline {subsubsection}{\numberline {4.3.2.1}Memory Controller Initialization}{27}{subsubsection.4.3.2.1}%
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\contentsline {subsubsection}{\numberline {4.3.2.2}Memory Module Training}{28}{subsubsection.4.3.2.2}%
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\contentsline {chapter}{\numberline {5}Virtualization of the operating system through firmware abstraction}{29}{chapter.5}%
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\contentsline {section}{\numberline {5.1}ACPI and abstraction of hardware control}{29}{section.5.1}%
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\contentsline {section}{\numberline {5.2}SMM as a hidden execution layer}{29}{section.5.2}%
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\contentsline {section}{\numberline {5.3}UEFI and persistence}{29}{section.5.3}%
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\contentsline {section}{\numberline {5.4}Intel and AMD: control beyond the OS}{30}{section.5.4}%
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\contentsline {section}{\numberline {5.5}The OS as a virtualized environment}{30}{section.5.5}%
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\contentsline {chapter}{Conclusion}{31}{chapter*.2}%
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\contentsline {section}{\numberline {5.6}Summary of key points}{31}{section.5.6}%
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\contentsline {section}{\numberline {5.7}Call for action}{31}{section.5.7}%
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\contentsline {chapter}{Bibliography}{32}{section.5.7}%
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\contentsline {chapter}{List of Figures}{38}{chapter*.3}%
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\contentsline {chapter}{List of Listings}{39}{chapter*.3}%
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\contentsline {chapter}{GNU Free Documentation License}{40}{chapter*.5}%
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