2019-05-23 23:21:58 +02:00
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//----------------------------------------------------------------------------//
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2020-09-27 17:33:48 +02:00
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// OS on Kaleid //
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2019-05-23 23:21:58 +02:00
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// //
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// Desc: Basic Read Only ATA Long mode Driver //
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// //
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// //
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2021-02-18 19:54:35 +01:00
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// Copyright © 2018-2021 The OS/K Team //
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2019-05-23 23:21:58 +02:00
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// //
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// This file is part of OS/K. //
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// //
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// OS/K is free software: you can redistribute it and/or modify //
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// it under the terms of the GNU General Public License as published by //
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// the Free Software Foundation, either version 3 of the License, or //
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// any later version. //
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// //
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// OS/K is distributed in the hope that it will be useful, //
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// but WITHOUT ANY WARRANTY//without even the implied warranty of //
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
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// GNU General Public License for more details. //
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// //
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// You should have received a copy of the GNU General Public License //
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// along with OS/K. If not, see <https://www.gnu.org/licenses/>. //
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//----------------------------------------------------------------------------//
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#ifndef _KERNEL_H
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#include <kernel.h>
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#endif
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#ifndef _IO_ATA_H
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#define _IO_ATA_H
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#include <ke/idt.h>
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//----------------------------------------------------------------------------//
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2020-02-17 19:10:59 +01:00
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#define MASS_STORAGE_CLASS 0x1
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#define SERIAL_ATA_SUBCLASS 0x6
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2019-05-23 23:21:58 +02:00
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2020-02-20 01:01:50 +01:00
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enum
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{
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REG_H2D = 0x27, // Register FIS - host to device
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REG_D2H = 0x34, // Register FIS - device to host
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DMA_ACT = 0x39, // DMA activate FIS - device to host
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DMA_SETUP = 0x41, // DMA setup FIS - bidirectional
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DATA = 0x46, // Data FIS - bidirectional
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BIST = 0x58, // BIST activate FIS - bidirectional
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PIO_SETUP = 0x5F, // PIO setup FIS - device to host
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DEV_BITS = 0xA1 // Set device bits FIS - device to host
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};
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enum
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{
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IDENTIFY = 0xEC // CMD IDENTIFY
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};
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struct HostToDeviceFIS
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{
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// DWORD 0
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uchar type; // REG_H2D
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uchar pmport:4; // Port multiplier
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uchar reserved0:3; // Reserved
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uchar c:1; // 1: Command, 0: Control
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uchar command; // Command register
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uchar featurel; // Feature register, 7:0
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// DWORD 1
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uchar lba0; // LBA low register, 7:0
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uchar lba1; // LBA mid register, 15:8
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uchar lba2; // LBA high register, 23:16
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uchar device; // Device register
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// DWORD 2
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uchar lba3; // LBA register, 31:24
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uchar lba4; // LBA register, 39:32
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uchar lba5; // LBA register, 47:40
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uchar featureh; // Feature register, 15:8
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// DWORD 3
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uchar countl; // Count register, 7:0
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uchar counth; // Count register, 15:8
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uchar icc; // Isochronous command completion
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uchar control; // Control register
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// DWORD 4
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uchar reserved1[4]; // Reserved
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};
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struct DMASetupFIS
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{
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// DWORD 0
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uchar type; // DMA_SETUP
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uchar pmport:4; // Port multiplier
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uchar reserved0:1; // Reserved
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uchar d:1; // Data transfer direction, 1 - device to host
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uchar i:1; // Interrupt bit
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uchar a:1; // Auto-activate. Specifies if DMA Activate FIS
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// is needed
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uchar reserved1[2]; // Reserved
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//DWORD 1&2
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ulong DMAbufferID; // DMA Buffer Identifier.
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// Used to Identify DMA buffer in host memory.
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// SATA Spec says host specific and not in Spec.
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// Trying AHCI spec might work.
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//DWORD 3
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uint reserved2; // More reserved
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//DWORD 4
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uint DMAbufOffset; // Byte offset into buffer. First 2 bits must be 0
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//DWORD 5
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uint TransferCount; // Number of bytes to transfer. Bit 0 must be 0
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//DWORD 6
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uint reserved3; // Reserved
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};
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2020-02-13 15:51:28 +01:00
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//----------------------------------------------------------------------------//
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2020-02-17 19:10:59 +01:00
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void IoDetectATA(void);
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2019-05-23 23:21:58 +02:00
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void IoReadATA(void *sectorBuffer, char n, char first);
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void IoDumpSector(void);
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//----------------------------------------------------------------------------//
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#endif
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