2020-02-10 00:15:37 +01:00
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//----------------------------------------------------------------------------//
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// GNU GPL OS/K //
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// //
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2020-02-10 00:49:35 +01:00
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// Desc: PCI driver //
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2020-02-10 00:15:37 +01:00
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// //
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// //
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// Copyright © 2018-2020 The OS/K Team //
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// //
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// This file is part of OS/K. //
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// //
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// OS/K is free software: you can redistribute it and/or modify //
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// it under the terms of the GNU General Public License as published by //
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// the Free Software Foundation, either version 3 of the License, or //
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// any later version. //
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// //
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// OS/K is distributed in the hope that it will be useful, //
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// but WITHOUT ANY WARRANTY//without even the implied warranty of //
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
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// GNU General Public License for more details. //
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// //
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// You should have received a copy of the GNU General Public License //
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// along with OS/K. If not, see <https://www.gnu.org/licenses/>. //
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//----------------------------------------------------------------------------//
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#ifndef _KERNEL_H
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#include <kernel.h>
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#endif
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2020-02-11 23:47:02 +01:00
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2020-02-10 00:15:37 +01:00
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#ifndef _IO_PCI_H
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#define _IO_PCI_H
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2020-02-11 23:47:02 +01:00
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//
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// Device registers offsets
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//
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2020-02-17 18:47:23 +01:00
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#define PCI_REG_VENDOR 0x00
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#define PCI_REG_DEVICE 0x02
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#define PCI_REG_COMMAND 0x04
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#define PCI_REG_STATUS 0x06
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#define PCI_REG_REVISION 0x08
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#define PCI_REG_PROGIF 0x09
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#define PCI_REG_SUBCLASS 0x0A
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#define PCI_REG_CLASS 0x0B
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#define PCI_REG_CACHE_LINE_SIZE 0x0C
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#define PCI_REG_LATENCY_TIMER 0x0D
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#define PCI_REG_HEADER_TYPE 0x0E
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#define PCI_REG_BIST 0x0F
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2020-02-12 23:55:54 +01:00
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#define PCI_REG_BAR0 0x10
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#define PCI_REG_BAR1 0x14
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#define PCI_REG_BAR2 0x18
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#define PCI_REG_BAR3 0x1C
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#define PCI_REG_BAR4 0x20
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#define PCI_REG_BAR5 0x24
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//..
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#define PCI_REG_INTERRUPT_LINE 0x3C
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2020-02-11 23:47:02 +01:00
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//..
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2020-02-12 18:28:32 +01:00
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//----------------------------------------------------------------------------//
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2020-02-12 23:55:54 +01:00
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struct PciDev_t {
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2020-02-12 18:28:32 +01:00
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ushort vendorID;
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ushort deviceID;
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2020-02-17 18:47:23 +01:00
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uchar classID;
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uchar subclassID;
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2020-02-12 18:28:32 +01:00
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void* configAddr;
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2020-02-12 23:55:54 +01:00
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};
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2020-02-12 18:28:32 +01:00
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2020-02-11 23:47:02 +01:00
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//----------------------------------------------------------------------------//
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2020-02-10 00:15:37 +01:00
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2020-02-11 23:47:02 +01:00
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void IoInitPCI();
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2020-02-12 17:48:05 +01:00
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void IoPciEnumerate();
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2020-02-12 23:55:54 +01:00
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PciDev_t *IoPciGetDevice(ushort vendorID, ushort deviceID);
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2020-02-17 18:58:45 +01:00
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PciDev_t *IoPciGetDeviceByClass(uchar classID, uchar subclassID);
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2020-02-12 23:55:54 +01:00
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uchar IoPciReadConfigByte(PciDev_t *device, ushort offset);
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ushort IoPciReadConfigWord(PciDev_t *device, ushort offset);
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uint IoPciReadConfigDWord(PciDev_t *device, ushort offset);
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void IoPciWriteConfigByte(PciDev_t *device, ushort offset, uchar data);
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void IoPciWriteConfigWord(PciDev_t *device, ushort offset, ushort data);
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void IoPciWriteConfigDWord(PciDev_t *device, ushort offset, uint data);
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2020-02-10 00:15:37 +01:00
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#endif
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