Working static paging
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@ -25,30 +25,40 @@ enum
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MF_WRITETHR = 1 << 3,
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MF_CACHEDIS = 1 << 4,
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MF_ACCESSED = 1 << 5,
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MF_DIRTY = 1 << 6
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MF_DIRTY = 1 << 6,
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MF_HUGE = 1 << 7
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};
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#define RAM 8
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#define NB_4K 2
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//-----------
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volatile pdpe_t PML4[512] __attribute__((__aligned__(4096)));
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// First PDPE of our pml4
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volatile pde_t PDP[512] __attribute__((__aligned__(4096)));
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// First PDP of first_pdpe
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volatile pte_t PD[512 * RAM] __attribute__((__aligned__(4096)));
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volatile pde_t PD[512 * RAM] __attribute__((__aligned__(4096)));
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volatile pte_t PT[512 * NB_4K] __attribute__((__aligned__(4096)));
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void MmInitPaging(void)
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{
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memzero((void *)&PML4[0], sizeof(PML4));
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memzero((void *)&PDP[0], sizeof(PDP));
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memzero((void *)&PD[0], sizeof(PD));
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memzero((void *)&PT[0], sizeof(PT));
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for (int i = 0; i < 512 * RAM; i++) {
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PD[i] = ((ulong)i * 2048 * 1024) | MF_PRESENT | MF_READWRITE | 1 << 7;
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for (int i = 0; i < 512 * NB_4K; i++) {
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PT[i] = ((ulong)i * 4096) | MF_PRESENT | MF_READWRITE;
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}
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for (int i = 0; i < NB_4K; i++) {
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PD[i] = (ulong)(&PT[i*512])| MF_PRESENT | MF_READWRITE;
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}
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for (int i = NB_4K; i < 512 * RAM; i++) {
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PD[i] = ((ulong)i * 2048 * 1024) | MF_PRESENT | MF_READWRITE | MF_HUGE;
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}
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for (int i = 0; i < RAM; i++) {
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