//----------------------------------------------------------------------------//
//                           GNU GPL OS/K                                     //
//                                                                            //
//  Desc:     Basic Read Only ATA Long mode Driver                            //
//                                                                            //
//                                                                            //
//  Copyright © 2018-2020 The OS/K Team                                       //
//                                                                            //
//  This file is part of OS/K.                                                //
//                                                                            //
//  OS/K is free software: you can redistribute it and/or modify              //
//  it under the terms of the GNU General Public License as published by      //
//  the Free Software Foundation, either version 3 of the License, or         //
//  any later version.                                                        //
//                                                                            //
//  OS/K is distributed in the hope that it will be useful,                   //
//  but WITHOUT ANY WARRANTY//without even the implied warranty of            //
//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             //
//  GNU General Public License for more details.                              //
//                                                                            //
//  You should have received a copy of the GNU General Public License         //
//  along with OS/K.  If not, see <https://www.gnu.org/licenses/>.            //
//----------------------------------------------------------------------------//

#ifndef _KERNEL_H
#include <kernel.h>
#endif

#ifndef _IO_ATA_H
#define _IO_ATA_H

#include <ke/idt.h>

//----------------------------------------------------------------------------//

#define MASS_STORAGE_CLASS 0x1
#define SERIAL_ATA_SUBCLASS 0x6

enum
{
	REG_H2D    = 0x27,  // Register FIS - host to device
	REG_D2H    = 0x34,  // Register FIS - device to host
	DMA_ACT    = 0x39,  // DMA activate FIS - device to host
	DMA_SETUP  = 0x41,  // DMA setup FIS - bidirectional
	DATA       = 0x46,  // Data FIS - bidirectional
	BIST       = 0x58,  // BIST activate FIS - bidirectional
	PIO_SETUP  = 0x5F,  // PIO setup FIS - device to host
	DEV_BITS   = 0xA1   // Set device bits FIS - device to host
};

enum
{
	IDENTIFY = 0xEC     // CMD IDENTIFY
};

struct HostToDeviceFIS
{
	// DWORD 0
	uchar type;	            // REG_H2D

	uchar pmport:4;         // Port multiplier
	uchar reserved0:3;      // Reserved
	uchar c:1;              // 1: Command, 0: Control

	uchar command;          // Command register
	uchar featurel;         // Feature register, 7:0

	// DWORD 1
	uchar lba0;             // LBA low register, 7:0
	uchar lba1;             // LBA mid register, 15:8
	uchar lba2;             // LBA high register, 23:16
	uchar device;           // Device register

	// DWORD 2
	uchar lba3;             // LBA register, 31:24
	uchar lba4;             // LBA register, 39:32
	uchar lba5;             // LBA register, 47:40
	uchar featureh;         // Feature register, 15:8

	// DWORD 3
	uchar countl;           // Count register, 7:0
	uchar counth;           // Count register, 15:8
	uchar icc;              // Isochronous command completion
	uchar control;          // Control register

	// DWORD 4
	uchar reserved1[4];	// Reserved
};

struct DMASetupFIS
{
    // DWORD 0
    uchar type;             // DMA_SETUP

    uchar pmport:4;         // Port multiplier
    uchar reserved0:1;      // Reserved
    uchar d:1;              // Data transfer direction, 1 - device to host
    uchar i:1;              // Interrupt bit
    uchar a:1;              // Auto-activate. Specifies if DMA Activate FIS
                            // is needed

    uchar reserved1[2];      // Reserved

    //DWORD 1&2
    ulong DMAbufferID;      // DMA Buffer Identifier.
                            // Used to Identify DMA buffer in host memory.
                            // SATA Spec says host specific and not in Spec.
                            // Trying AHCI spec might work.

    //DWORD 3
    uint reserved2;         // More reserved

    //DWORD 4
    uint DMAbufOffset;      // Byte offset into buffer. First 2 bits must be 0

    //DWORD 5
    uint TransferCount;     // Number of bytes to transfer. Bit 0 must be 0

    //DWORD 6
    uint reserved3;         // Reserved
};

//----------------------------------------------------------------------------//

void IoDetectATA(void);
void IoReadATA(void *sectorBuffer, char n, char first);
void IoDumpSector(void);

//----------------------------------------------------------------------------//

#endif