190 lines
6.4 KiB
C
190 lines
6.4 KiB
C
//----------------------------------------------------------------------------//
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// GNU GPL OS/K //
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// //
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// Desc: Interrupt related functions //
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// //
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// //
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// Copyright © 2018-2019 The OS/K Team //
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// //
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// This file is part of OS/K. //
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// //
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// OS/K is free software: you can redistribute it and/or modify //
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// it under the terms of the GNU General Public License as published by //
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// the Free Software Foundation, either version 3 of the License, or //
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// any later version. //
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// //
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// OS/K is distributed in the hope that it will be useful, //
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// but WITHOUT ANY WARRANTY//without even the implied warranty of //
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
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// GNU General Public License for more details. //
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// //
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// You should have received a copy of the GNU General Public License //
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// along with OS/K. If not, see <https://www.gnu.org/licenses/>. //
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//----------------------------------------------------------------------------//
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#include <kernel/base.h>
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#include <kernel/idt.h>
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#include <kernel/boot.h>
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#include <kernel/iomisc.h>
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#include <extras/buf.h>
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IdtEntry_t idt[256] = { 0 };
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IdtPtr_t idtPtr;
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IRQList_t irqList = { 0 };
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//
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// Registers an isr with his IRQ to handle driver interrupts
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//
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void IdtRegisterIrq(void (*isr)(void), uchar irq, uchar flags)
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{
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KalAssert(idt[0].flags==0); // IDT uninitialized
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irqList.entry[irqList.n].isr = isr;
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irqList.entry[irqList.n].irq = irq;
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irqList.entry[irqList.n].flags = flags;
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irqList.n++;
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}
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//
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// Installs the IDT in order to activate the interrupts handling
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//
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void IdtSetup(void)
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{
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// XXX detect the APIC with cpuid !
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DisablePIC();
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ushort codeSeg = (ushort)(ulong)BtLoaderInfo.codeSegment;
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// Set IDT ptr
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idtPtr.limit = (sizeof(IdtEntry_t) * 256) - 1;
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idtPtr.base = &idt;
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// Set IDT Exception Gates
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IdtSetGate(0, (ulong)isr0, codeSeg, 0x8E);
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IdtSetGate(1, (ulong)isr1, codeSeg, 0x8E);
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IdtSetGate(2, (ulong)isr2, codeSeg, 0x8E);
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IdtSetGate(3, (ulong)isr3, codeSeg, 0x8E);
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IdtSetGate(4, (ulong)isr4, codeSeg, 0x8E);
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IdtSetGate(5, (ulong)isr5, codeSeg, 0x8E);
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IdtSetGate(6, (ulong)isr6, codeSeg, 0x8E);
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IdtSetGate(7, (ulong)isr7, codeSeg, 0x8E);
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IdtSetGate(8, (ulong)isr8, codeSeg, 0x8E);
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IdtSetGate(9, (ulong)isr9, codeSeg, 0x8E);
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IdtSetGate(10, (ulong)isr10, codeSeg, 0x8E);
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IdtSetGate(11, (ulong)isr11, codeSeg, 0x8E);
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IdtSetGate(12, (ulong)isr12, codeSeg, 0x8E);
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IdtSetGate(13, (ulong)isr13, codeSeg, 0x8E);
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IdtSetGate(14, (ulong)isr14, codeSeg, 0x8E);
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IdtSetGate(15, (ulong)isr15, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(16, (ulong)isr16, codeSeg, 0x8E);
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IdtSetGate(17, (ulong)isr17, codeSeg, 0x8E);
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IdtSetGate(18, (ulong)isr18, codeSeg, 0x8E);
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IdtSetGate(19, (ulong)isr19, codeSeg, 0x8E);
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IdtSetGate(20, (ulong)isr20, codeSeg, 0x8E);
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IdtSetGate(21, (ulong)isr21, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(22, (ulong)isr22, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(23, (ulong)isr23, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(24, (ulong)isr24, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(25, (ulong)isr25, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(26, (ulong)isr26, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(27, (ulong)isr27, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(28, (ulong)isr28, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(29, (ulong)isr29, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(30, (ulong)isr30, codeSeg, 0x8E); // INTEL RESERVED
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// Set the IRQ Driver Gates
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for (int i = 0 ; i < irqList.n ; i++) {
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IdtSetGate(irqList.entry[irqList.n].irq,
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(ulong)irqList.entry[irqList.n].isr,
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codeSeg,
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irqList.entry[irqList.n].flags
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);
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}
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// Load IDT
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CpuIdtInit();
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DebugLog("[IdtSetup] Initialized !\n");
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}
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//
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// Set an interrupt gate
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//
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void IdtSetGate(uchar rank, ulong base, ushort selector, uchar flags)
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{
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// Set Base Address
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idt[rank].baseLow = base & 0xFFFF;
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idt[rank].baseMid = (base >> 16) & 0xFFFF;
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idt[rank].baseHigh = (base >> 32) & 0xFFFFFFFF;
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// Set Selector
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idt[rank].selector = selector;
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idt[rank].flags = flags;
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// Set Reserved Areas to Zero
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idt[rank].reservedIst = 0;
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idt[rank].reserved = 0;
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}
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//
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// Disables the PIC to activate the APIC
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//
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static void DisablePIC(void)
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{
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// Set ICW1
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IoWriteByteOnPort(0x20, 0x11);
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IoWriteByteOnPort(0xa0, 0x11);
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// Set ICW2 (IRQ base offsets)
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IoWriteByteOnPort(0x21, 0xe0);
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IoWriteByteOnPort(0xa1, 0xe8);
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// Set ICW3
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IoWriteByteOnPort(0x21, 4);
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IoWriteByteOnPort(0xa1, 2);
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// Set ICW4
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IoWriteByteOnPort(0x21, 1);
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IoWriteByteOnPort(0xa1, 1);
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// Set OCW1 (interrupt masks)
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IoWriteByteOnPort(0x21, 0xff);
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IoWriteByteOnPort(0xa1, 0xff);
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// ENABLING LOCAL APIC
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uint *val = (void*)0xfee000f0;
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*val |= (1<<8);
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}
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//
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// Ends the current interrupt handling
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//
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static void SendEOItoPIC(uchar isr)
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{
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if(isr >= 8)
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IoWriteByteOnPort(0xa0,0x20);
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IoWriteByteOnPort(0x20,0x20);
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}
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//
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// The main exception handler
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//
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void IdtHandler(ulong intNo)
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{
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int irrecoverable = 0;
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char *exceptionMsg = "Unhandled ISR exception";
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if (intNo == 0 || intNo == 6 || intNo == 8 || intNo == 13) irrecoverable++;
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if (intNo < 32) exceptionMsg = IsrExceptions[intNo];
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if (irrecoverable) {
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KeStartPanic("[ISR 0x%x] Irrecoverable %s\n", intNo, exceptionMsg);
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} else {
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bprintf(BStdOut, "[ISR 0x%x] %s\n", intNo, exceptionMsg);
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SendEOItoPIC(intNo);
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}
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}
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