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coreboot-kgpe-d16/util/inteltool/pcr.h

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inteltool: Support for nasty Primary to Sideband Bridge (P2SB) The Primary to Sideband Bridge (P2SB) is the interface to Private Con- figuration Registers (PCR) including GPIO configuration. Of course, access is restricted to Intel partners and criminals, so the PCI device is hidden from the OS. Probably we only need to fetch the SBREG_BAR address and can hide the PCI device again after that. Change-Id: Ic121a09f021708aab82ae4b9d76d6c3c6fb884fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-05 17:39:57 +02:00
/*
* inteltool - dump all registers on an Intel CPU + chipset based system.
*
* Copyright (C) 2017 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef INTELTOOL_PCR_H
#define INTELTOOL_PCR_H 1
#include <stdint.h>
#include "inteltool.h"
#define SBBAR_SIZE (16 * MiB)
#define PCR_PORT_SIZE (64 * KiB)
uint32_t read_pcr32(uint8_t port, uint16_t offset);
inteltool: Add dumping of full PCR ports SoCs from Skylake on have many settings as so called private con- figuration registers (PCRs). These are organized as 256 ports with a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's BAR to access them. Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19593 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-13 21:58:52 +01:00
void print_pcr_ports(struct pci_dev *sb, const uint8_t *ports, size_t count);
inteltool: Support for nasty Primary to Sideband Bridge (P2SB) The Primary to Sideband Bridge (P2SB) is the interface to Private Con- figuration Registers (PCR) including GPIO configuration. Of course, access is restricted to Intel partners and criminals, so the PCI device is hidden from the OS. Probably we only need to fetch the SBREG_BAR address and can hide the PCI device again after that. Change-Id: Ic121a09f021708aab82ae4b9d76d6c3c6fb884fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-05 17:39:57 +02:00
void pcr_init(struct pci_dev *sb);
void pcr_cleanup(void);
#endif