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coreboot-kgpe-d16/src/soc/nvidia/tegra210/Kconfig

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nvidia/tegra210: add new SoC This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I81853434600390d643160fe57554495b2bfe60ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-22 19:41:29 +02:00
config SOC_NVIDIA_TEGRA210
bool
default n
select ARCH_BOOTBLOCK_ARMV4
select ARCH_VERSTAGE_ARMV4
select ARCH_ROMSTAGE_ARMV4
select ARCH_RAMSTAGE_ARMV8_64
select ARCH_ARM64_CPU_CORTEX_A57
select ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT
select BOOTBLOCK_CONSOLE
select GIC
select HAVE_MONOTONIC_TIMER
select GENERIC_UDELAY
select HAVE_HARD_RESET
select HAVE_UART_SPECIAL
select ARM_BOOTBLOCK_CUSTOM
select ARM64_USE_ARM_TRUSTED_FIRMWARE
select HAS_PRECBMEM_TIMESTAMP_REGION
select CHROMEOS_RAMOOPS_NON_ACPI
select GENERIC_GPIO_LIB
if SOC_NVIDIA_TEGRA210
config MAINBOARD_DO_DSI_INIT
bool "Use dsi graphics interface"
depends on MAINBOARD_DO_NATIVE_VGA_INIT
default n
help
Initialize dsi display
config MAINBOARD_DO_SOR_INIT
bool "Use dp graphics interface"
depends on MAINBOARD_DO_NATIVE_VGA_INIT
default n
help
Initialize dp display
config BOOTBLOCK_CPU_INIT
string
default "soc/nvidia/tegra210/bootblock.c"
help
CPU/SoC-specific bootblock code. This is useful if the
bootblock must load microcode or copy data from ROM before
searching for the bootblock.
config MAX_CPUS
int
default 4
choice CONSOLE_SERIAL_TEGRA210_UART_CHOICES
prompt "Serial Console UART"
default CONSOLE_SERIAL_TEGRA210_UARTA
Kconfig: Fix references to obsolete symbols These are all Kconfig symbols that have been removed or renamed. USE_PRINTK_IN_CAR was removed in commit 8c4f31b3 Drop the USE_PRINTK_IN_CAR option. It's a bogus decision... DYNAMIC_CBMEM was removed in commit e2b0affd Remove Kconfig variable that has no effect MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc Remove Kconfig variable that has no effect CACHE_ROM was removed in commit 4337020b Remove CACHE_ROM. SMM_MODULES was removed in commit 44cbe10f smm: Merge configs SMM_MODULES and SMM_TSEG INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218 soc/fsp_baytrail: Fix use of microcode-related Kconfig variables CAR_MIGRATION was removed in commit cbf5bdfe CBMEM: Always select CAR_MIGRATION REQUIRES_BLOB was removed in commit 70c85eab build system: Retire REQUIRES_BLOB CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b uart: Redefine Kconfig options CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit afa7b13b - uart: Redefine Kconfig options Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10766 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-02 07:09:42 +02:00
depends on CONSOLE_SERIAL
nvidia/tegra210: add new SoC This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I81853434600390d643160fe57554495b2bfe60ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-22 19:41:29 +02:00
config CONSOLE_SERIAL_TEGRA210_UARTA
bool "UARTA"
help
Serial console on UART A.
config CONSOLE_SERIAL_TEGRA210_UARTB
bool "UARTB"
help
Serial console on UART B.
config CONSOLE_SERIAL_TEGRA210_UARTC
bool "UARTC"
help
Serial console on UART C.
config CONSOLE_SERIAL_TEGRA210_UARTD
bool "UARTD"
help
Serial console on UART D.
config CONSOLE_SERIAL_TEGRA210_UARTE
bool "UARTE"
help
Serial console on UART E.
endchoice
config CONSOLE_SERIAL_TEGRA210_UART_ADDRESS
hex
Kconfig: Fix references to obsolete symbols These are all Kconfig symbols that have been removed or renamed. USE_PRINTK_IN_CAR was removed in commit 8c4f31b3 Drop the USE_PRINTK_IN_CAR option. It's a bogus decision... DYNAMIC_CBMEM was removed in commit e2b0affd Remove Kconfig variable that has no effect MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc Remove Kconfig variable that has no effect CACHE_ROM was removed in commit 4337020b Remove CACHE_ROM. SMM_MODULES was removed in commit 44cbe10f smm: Merge configs SMM_MODULES and SMM_TSEG INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218 soc/fsp_baytrail: Fix use of microcode-related Kconfig variables CAR_MIGRATION was removed in commit cbf5bdfe CBMEM: Always select CAR_MIGRATION REQUIRES_BLOB was removed in commit 70c85eab build system: Retire REQUIRES_BLOB CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b uart: Redefine Kconfig options CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit afa7b13b - uart: Redefine Kconfig options Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10766 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-02 07:09:42 +02:00
depends on CONSOLE_SERIAL
nvidia/tegra210: add new SoC This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I81853434600390d643160fe57554495b2bfe60ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-22 19:41:29 +02:00
default 0x70006000 if CONSOLE_SERIAL_TEGRA210_UARTA
default 0x70006040 if CONSOLE_SERIAL_TEGRA210_UARTB
default 0x70006200 if CONSOLE_SERIAL_TEGRA210_UARTC
default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD
default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE
help
Map the UART names to the respective MMIO addres.
config BOOTROM_SDRAM_INIT
bool "SoC BootROM does SDRAM init with full BCT"
default n
help
Use during Foster LPDDR4 bringup.
config TRUSTZONE_CARVEOUT_SIZE_MB
hex "Size of Trust Zone region"
default 0x14
help
Size of Trust Zone area in MiB to reserve in memory map.
t210: Add TZDRAM_BASE param to BL31_MAKEARGS 1. Make TTB_SIZE Kconfig option 2. Add Kconfig option for maximum secure component size 3. Add check in Makefile to ensure that Trustzone area is big enough to hold TTB and secure components 4. Calculate TZDRAM_BASE depending upon TTB_SIZE and TZ_CARVEOUT_SIZE BUG=chrome-os-partner:42319 BRANCH=None Change-Id: I9ceb46ceedc931826657e5a0f6fc2b1886526bf8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a425d4978a467b157ea5d71e600242ebf427b5bb Original-Change-Id: I152a38830773d85aafab49c92cef945b7c4eb62c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284074 Original-Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10878 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-08 06:35:56 +02:00
config TTB_SIZE_MB
hex "Size of TTB"
default 0x4
help
Maximum size of Translation Table Buffer in MiB.
config SEC_COMPONENT_SIZE_MB
hex "Size of resident EL3 components"
default 0x10
help
Maximum size of resident EL3 components in MiB including BL31 and
Secure OS.
nvidia/tegra210: add new SoC This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I81853434600390d643160fe57554495b2bfe60ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-22 19:41:29 +02:00
# Default to 700MHz. This value is based on nv bootloader setting.
config PLLX_KHZ
Kconfig whitespace cleanup: Change leading spaces to tabs Change-Id: Icab6bd9f55f086da7b51ae463f34e29366d50e1a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10764 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-02 03:38:29 +02:00
int
default 700000
nvidia/tegra210: add new SoC This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I81853434600390d643160fe57554495b2bfe60ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-22 19:41:29 +02:00
endif
config HAVE_MTC
bool "Add external Memory controller Training Code binary"
default n
depends on USE_BLOBS
help
Select this option to add emc training firmware
if HAVE_MTC
config MTC_FILE
string "tegra mtc firmware filename"
default "tegra_mtc.bin"
help
The filename of the mtc firmware
config MTC_DIRECTORY
string "Directory where MTC firmware file is located"
default "."
help
Path to directory where MTC firmware file is located.
config MTC_ADDRESS
hex
default 0x81000000
help
The DRAM location where MTC firmware to be loaded in. This location
needs to be consistent with the location defined in tegra_mtc.ld
endif # HAVE_MTC
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