88 lines
2.6 KiB
C
88 lines
2.6 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <soc/addressmap.h>
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#include "pmc.h"
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#include "power.h"
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static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE;
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static int partition_powered(int id)
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{
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return read32(&pmc->pwrgate_status) & (0x1 << id);
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}
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static void power_ungate_partition(uint32_t id)
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{
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printk(BIOS_INFO, "Ungating power partition %d.\n", id);
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if (!partition_powered(id)) {
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uint32_t pwrgate_toggle = read32(&pmc->pwrgate_toggle);
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pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK);
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pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT);
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pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START;
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write32(pwrgate_toggle, &pmc->pwrgate_toggle);
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// Wait for the request to be accepted.
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while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START)
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;
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printk(BIOS_DEBUG, "Power gate toggle request accepted.\n");
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// Wait for the partition to be powered.
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while (!partition_powered(id))
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;
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}
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printk(BIOS_INFO, "Ungated power partition %d.\n", id);
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}
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void power_enable_cpu_rail(void)
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{
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// Set the power gate timer multiplier to 8 (why 8?).
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uint32_t pwrgate_timer_mult = read32(&pmc->pwrgate_timer_mult);
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pwrgate_timer_mult |= (0x3 << 0);
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/*
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* From U-Boot:
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* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
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* set it for 5ms as per SysEng (102MHz/5mS = 510000).
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*/
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write32(510000, &pmc->cpupwrgood_timer);
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power_ungate_partition(POWER_PARTID_CRAIL);
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uint32_t cntrl = read32(&pmc->cntrl);
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cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY;
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cntrl |= PMC_CNTRL_CPUPWRREQ_OE;
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write32(cntrl, &pmc->cntrl);
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}
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void power_ungate_cpu(void)
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{
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// Ungate power to the non-core parts of the fast cluster.
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power_ungate_partition(POWER_PARTID_C0NC);
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// Ungate power to CPU0 in the fast cluster.
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power_ungate_partition(POWER_PARTID_CE0);
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}
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