2010-11-09 23:18:28 +01:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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2013-02-23 18:37:27 +01:00
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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2010-11-09 23:18:28 +01:00
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*/
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/*
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* ISA portions taken from QEMU acpi-dsdt.dsl.
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*/
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#define LNKA INTA
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#define LNKB INTB
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#define LNKC INTC
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#define LNKD INTD
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/*
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* For simplicity map LNK[E-H] to LNK[A-D].
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* This also means we are 82C596 compatible.
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* Needs 0:11.0 0x46[4] set to 0.
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*/
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#define LNKE INTA
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#define LNKF INTB
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#define LNKG INTC
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#define LNKH INTD
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DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
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{
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Name(APIC, 0) // 0=>8259, 1=>IOAPIC
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/* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method(_PIC, 1)
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{
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// Remember the OS' IRQ routing choice.
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Store(Arg0, APIC)
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}
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/* _PR CPU0 is dynamically supplied by SSDT */
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2010-11-24 21:03:09 +01:00
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/* We define 3 power states:
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2010-11-09 23:18:28 +01:00
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* - S0 which is fully on
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2010-11-24 21:03:09 +01:00
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* - S3 which is suspend to ram
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2010-11-09 23:18:28 +01:00
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* - S5 which is soft off
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*
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* Package contents:
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* ofs len desc
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* 0 1 Value for PM1a_CNT.SLP_TYP register to enter this system state.
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* 1 1 Value for PM1b_CNT.SLP_TYP register to enter this system state. To enter any
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* given state, OSPM must write the PM1a_CNT.SLP_TYP register before the
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* PM1b_CNT.SLP_TYP register.
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* 2 2 Reserved
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*/
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Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
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2010-11-24 21:03:09 +01:00
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Name (\_S3, Package () { 0x01, 0x01, 0x00, 0x00 })
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2010-11-09 23:18:28 +01:00
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Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
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/* Root of the bus hierarchy */
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Scope (\_SB)
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{
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/* Top PCI device */
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Device (PCI0)
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{
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Name (_HID, EisaId ("PNP0A03"))
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Name (_ADR, 0x00180000)
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Name (_BBN, 0x00)
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Name (APRT, Package() {
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/* AGP? */
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Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
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Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
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Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 },
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Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 },
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/* PCIe graphics bridge */
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Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B },
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Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
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Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
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Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
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/* PCIe bridge */
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Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },
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Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 },
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Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 },
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Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B },
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/* SATA */
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Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 },
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/* IDE */
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Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x15 },
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/* USB */
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Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 },
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Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 },
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Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
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Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 },
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/* PCI bridge */
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Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 },
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Package (0x04) { 0x0013FFFF, 0x01, 0x00, 0x14 },
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Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x14 },
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Package (0x04) { 0x0013FFFF, 0x03, 0x00, 0x14 },
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})
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Name (PPRT, Package() {
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/* ?? */
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Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 },
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Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 },
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Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 },
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Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 },
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/* PCIe graphics bridge */
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Package (0x04) { 0x0002FFFF, 0x00, LNKH, 0x00 },
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Package (0x04) { 0x0002FFFF, 0x01, LNKH, 0x00 },
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Package (0x04) { 0x0002FFFF, 0x02, LNKH, 0x00 },
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Package (0x04) { 0x0002FFFF, 0x03, LNKH, 0x00 },
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/* PCIe bridge */
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Package (0x04) { 0x0003FFFF, 0x00, LNKH, 0x00 },
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Package (0x04) { 0x0003FFFF, 0x01, LNKH, 0x00 },
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Package (0x04) { 0x0003FFFF, 0x02, LNKH, 0x00 },
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Package (0x04) { 0x0003FFFF, 0x03, LNKH, 0x00 },
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/* SATA */
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Package (0x04) { 0x000FFFFF, 0x01, LNKB, 0x00 },
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/* USB */
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Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 },
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Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 },
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Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 },
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Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 },
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/* PCI bridge */
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Package (0x04) { 0x0013FFFF, 0x00, LNKD, 0x00 },
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Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 },
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Package (0x04) { 0x0013FFFF, 0x02, LNKD, 0x00 },
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Package (0x04) { 0x0013FFFF, 0x03, LNKD, 0x00 },
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})
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/* PCI Routing Table */
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Method (_PRT, 0, NotSerialized)
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{
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If (APIC)
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{
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Return (APRT)
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}
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Return (PPRT)
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}
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Device (PEGG)
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{
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Name (_ADR, 0x00020000)
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Name (APRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
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})
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Name (PPRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
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})
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Method (_PRT, 0, NotSerialized)
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{
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If (APIC)
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{
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Return (APRT)
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}
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Return (PPRT)
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}
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}
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Device (PEX0)
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{
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Name (_ADR, 0x00030000)
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Name (APRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
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})
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Name (PPRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
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})
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Method (_PRT, 0, NotSerialized)
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{
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If (APIC)
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{
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Return (APRT)
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}
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Return (PPRT)
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}
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}
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Device (PEX1)
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{
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Name (_ADR, 0x00030001)
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Name (APRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
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})
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Name (PPRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
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})
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Method (_PRT, 0, NotSerialized)
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{
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If (APIC)
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{
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Return (APRT)
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}
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Return (PPRT)
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}
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}
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Device (PEX2)
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{
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Name (_ADR, 0x00030002)
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Name (APRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
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})
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Name (PPRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
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})
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Method (_PRT, 0, NotSerialized)
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{
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If (APIC)
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{
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Return (APRT)
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}
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Return (PPRT)
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}
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}
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Device (PCI6)
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{
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Name (_ADR, 0x00130000)
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Name (APRT, Package () {
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Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* IRQ17 */
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})
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Name (PPRT, Package () {
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Package (0x04) { 0x0001FFFF, 0x00, LNKB, 0x00 },
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})
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Method (_PRT, 0, NotSerialized)
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{
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If (APIC)
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{
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Return (APRT)
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}
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Return (PPRT)
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}
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}
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Device (PCI7)
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{
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Name (_ADR, 0x00130001)
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Name (APRT, Package () {
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/* PCI slot 1 */
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Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 },
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Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
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Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
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|
|
Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
|
|
|
|
|
|
|
|
|
|
/* PCI slot 2 */
|
|
|
|
|
Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 },
|
|
|
|
|
Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
|
|
|
|
|
Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
|
|
|
|
|
Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
|
|
|
|
|
|
|
|
|
|
/* PCI slot 3 */
|
|
|
|
|
Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 },
|
|
|
|
|
Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x13 },
|
|
|
|
|
Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x10 },
|
|
|
|
|
Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x11 },
|
|
|
|
|
|
|
|
|
|
/* PCI slot 4 */
|
|
|
|
|
Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x13 },
|
|
|
|
|
Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x10 },
|
|
|
|
|
Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x11 },
|
|
|
|
|
Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x12 },
|
|
|
|
|
})
|
|
|
|
|
Name (PPRT, Package () {
|
|
|
|
|
/* PCI slot 1 */
|
|
|
|
|
Package (0x04) { 0x0006FFFF, 0x00, LNKA, 0x00 },
|
|
|
|
|
Package (0x04) { 0x0006FFFF, 0x01, LNKB, 0x00 },
|
|
|
|
|
Package (0x04) { 0x0006FFFF, 0x02, LNKC, 0x00 },
|
|
|
|
|
Package (0x04) { 0x0006FFFF, 0x03, LNKD, 0x00 },
|
|
|
|
|
|
|
|
|
|
/* PCI slot 2 */
|
|
|
|
|
Package (0x04) { 0x0007FFFF, 0x00, LNKB, 0x00 },
|
|
|
|
|
Package (0x04) { 0x0007FFFF, 0x01, LNKC, 0x00 },
|
|
|
|
|
Package (0x04) { 0x0007FFFF, 0x02, LNKD, 0x00 },
|
|
|
|
|
Package (0x04) { 0x0007FFFF, 0x03, LNKA, 0x00 },
|
|
|
|
|
|
|
|
|
|
/* PCI slot 3 */
|
|
|
|
|
Package (0x04) { 0x0008FFFF, 0x00, LNKC, 0x00 },
|
|
|
|
|
Package (0x04) { 0x0008FFFF, 0x01, LNKD, 0x00 },
|
|
|
|
|
Package (0x04) { 0x0008FFFF, 0x02, LNKA, 0x00 },
|
|
|
|
|
Package (0x04) { 0x0008FFFF, 0x03, LNKB, 0x00 },
|
|
|
|
|
|
|
|
|
|
/* PCI slot 4 */
|
|
|
|
|
Package (0x04) { 0x0009FFFF, 0x00, LNKD, 0x00 },
|
|
|
|
|
Package (0x04) { 0x0009FFFF, 0x01, LNKA, 0x00 },
|
|
|
|
|
Package (0x04) { 0x0009FFFF, 0x02, LNKB, 0x00 },
|
|
|
|
|
Package (0x04) { 0x0009FFFF, 0x03, LNKC, 0x00 },
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
Method (_PRT, 0, NotSerialized)
|
|
|
|
|
{
|
|
|
|
|
If (APIC)
|
|
|
|
|
{
|
|
|
|
|
Return (APRT)
|
|
|
|
|
}
|
|
|
|
|
Return (PPRT)
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Device (SBRG) { /* southbridge */
|
|
|
|
|
Name (_ADR, 0x00110000)
|
2010-11-24 21:03:09 +01:00
|
|
|
OperationRegion (PCIC, PCI_Config, 0x0, 0x100)
|
2010-11-09 23:18:28 +01:00
|
|
|
|
|
|
|
|
/* PS/2 keyboard (seems to be important for WinXP install) */
|
|
|
|
|
Device (KBD)
|
|
|
|
|
{
|
|
|
|
|
Name (_HID, EisaId ("PNP0303"))
|
|
|
|
|
Method (_STA, 0, NotSerialized)
|
|
|
|
|
{
|
|
|
|
|
Return (0x0f)
|
|
|
|
|
}
|
|
|
|
|
Method (_CRS, 0, NotSerialized)
|
|
|
|
|
{
|
|
|
|
|
Name (TMP, ResourceTemplate () {
|
|
|
|
|
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
|
|
|
|
|
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
|
|
|
|
|
IRQNoFlags () {1}
|
|
|
|
|
})
|
|
|
|
|
Return (TMP)
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* PS/2 mouse */
|
|
|
|
|
Device (MOU)
|
|
|
|
|
{
|
|
|
|
|
Name (_HID, EisaId ("PNP0F13"))
|
|
|
|
|
Method (_STA, 0, NotSerialized)
|
|
|
|
|
{
|
|
|
|
|
Return (0x0f)
|
|
|
|
|
}
|
|
|
|
|
Method (_CRS, 0, NotSerialized)
|
|
|
|
|
{
|
|
|
|
|
Name (TMP, ResourceTemplate () {
|
|
|
|
|
IRQNoFlags () {12}
|
|
|
|
|
})
|
|
|
|
|
Return (TMP)
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Parallel port */
|
|
|
|
|
Device (LPT0)
|
|
|
|
|
{
|
|
|
|
|
Name (_HID, EisaId ("PNP0401"))
|
|
|
|
|
Method (_STA, 0, NotSerialized)
|
|
|
|
|
{
|
|
|
|
|
Return (0x0f)
|
|
|
|
|
}
|
|
|
|
|
Method (_CRS, 0, NotSerialized)
|
|
|
|
|
{
|
|
|
|
|
Name (TMP, ResourceTemplate () {
|
|
|
|
|
IO (Decode16, 0x0378, 0x0378, 0x01, 0x08)
|
|
|
|
|
IO (Decode16, 0x0778, 0x0778, 0x01, 0x08)
|
|
|
|
|
IRQNoFlags () {7}
|
|
|
|
|
DMA (Compatibility, NotBusMaster, Transfer8) {3}
|
|
|
|
|
})
|
|
|
|
|
Return (TMP)
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2010-11-17 17:27:06 +01:00
|
|
|
Device(MBRS) {
|
|
|
|
|
Name (_HID, EisaId ("PNP0C02"))
|
|
|
|
|
Name (_UID, 0x01)
|
|
|
|
|
|
|
|
|
|
External(_CRS) /* Resource Template in SSDT */
|
|
|
|
|
}
|
|
|
|
|
|
2010-11-09 23:18:28 +01:00
|
|
|
External(TOM1) /* top of memory below 4GB */
|
|
|
|
|
|
|
|
|
|
Method(_CRS, 0) {
|
|
|
|
|
Name(TMP, ResourceTemplate() {
|
|
|
|
|
WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
|
|
|
|
|
0x0000, // Granularity
|
|
|
|
|
0x0000, // Range Minimum
|
|
|
|
|
0x00FF, // Range Maximum
|
|
|
|
|
0x0000, // Translation Offset
|
|
|
|
|
0x0100, // Length
|
|
|
|
|
,,
|
|
|
|
|
)
|
|
|
|
|
IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
|
|
|
|
|
|
|
|
|
|
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
|
|
|
|
0x0000, /* address granularity */
|
|
|
|
|
0x0000, /* range minimum */
|
|
|
|
|
0x0CF7, /* range maximum */
|
|
|
|
|
0x0000, /* translation */
|
|
|
|
|
0x0CF8 /* length */
|
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
|
|
|
|
0x0000, /* address granularity */
|
|
|
|
|
0x0D00, /* range minimum */
|
|
|
|
|
0xFFFF, /* range maximum */
|
|
|
|
|
0x0000, /* translation */
|
|
|
|
|
0xF300 /* length */
|
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
/* memory space for PCI BARs below 4GB */
|
|
|
|
|
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
|
|
|
|
|
})
|
|
|
|
|
CreateDWordField(TMP, MMIO._BAS, MM1B)
|
|
|
|
|
CreateDWordField(TMP, MMIO._LEN, MM1L)
|
|
|
|
|
/*
|
|
|
|
|
* Declare memory between TOM1 and 4GB as available
|
|
|
|
|
* for PCI MMIO.
|
|
|
|
|
*
|
|
|
|
|
* Use ShiftLeft to avoid 64bit constant (for XP).
|
|
|
|
|
* This will work even if the OS does 32bit arithmetic, as
|
|
|
|
|
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
|
|
|
|
* result as 64bit (0x100000000 - TOM1).
|
|
|
|
|
*/
|
|
|
|
|
Store(TOM1, MM1B)
|
|
|
|
|
ShiftLeft(0x10000000, 4, Local0)
|
|
|
|
|
Subtract(Local0, TOM1, Local0)
|
|
|
|
|
Store(Local0, MM1L)
|
|
|
|
|
|
|
|
|
|
Return(TMP)
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2010-11-24 21:03:09 +01:00
|
|
|
Field (PCI0.SBRG.PCIC, ByteAcc, NoLock, Preserve)
|
2010-11-09 23:18:28 +01:00
|
|
|
{
|
2010-11-24 21:03:09 +01:00
|
|
|
Offset (0x55),
|
2010-11-09 23:18:28 +01:00
|
|
|
/*
|
|
|
|
|
* Offset 0x55:
|
|
|
|
|
* 3-0: reserved
|
|
|
|
|
* 7-4: PCI INTA# routing
|
|
|
|
|
* Offset 0x56:
|
|
|
|
|
* 3-0: PCI INTB# routing
|
|
|
|
|
* 7-4: PCI INTC# routing
|
|
|
|
|
* Offset 0x57:
|
|
|
|
|
* 3-0: reserved
|
|
|
|
|
* 7-4: PCI INTD# routing
|
|
|
|
|
*
|
|
|
|
|
* Valid values for routing link:
|
|
|
|
|
* 0: disabled
|
|
|
|
|
* 2,8,13: reserved
|
|
|
|
|
* 1,3-7,9-12,14,15: corresponding irq
|
|
|
|
|
*/
|
|
|
|
|
, 4,
|
|
|
|
|
PINA, 4,
|
|
|
|
|
PINB, 4,
|
|
|
|
|
PINC, 4,
|
|
|
|
|
, 4,
|
|
|
|
|
PIND, 4,
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Name(IRQB, ResourceTemplate(){
|
|
|
|
|
IRQ(Level,ActiveLow,Shared){15}
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
Name(IRQP, ResourceTemplate(){
|
|
|
|
|
IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 6, 7, 10, 11, 12}
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
/* adapted from ma78gm/dsdt.asl */
|
|
|
|
|
#define PCI_INTX_DEV(intx, pinx, uid) \
|
|
|
|
|
Device(intx) { \
|
|
|
|
|
Name(_HID, EISAID("PNP0C0F")) \
|
|
|
|
|
Name(_UID, uid) \
|
|
|
|
|
\
|
|
|
|
|
Method(_STA, 0) { \
|
|
|
|
|
if (pinx) { \
|
|
|
|
|
Return(0x0B) \
|
|
|
|
|
} \
|
|
|
|
|
Return(0x09) \
|
|
|
|
|
} \
|
|
|
|
|
\
|
|
|
|
|
Method(_DIS ,0) { \
|
|
|
|
|
Store(0, pinx) \
|
|
|
|
|
} \
|
|
|
|
|
\
|
|
|
|
|
Method(_PRS ,0) { \
|
|
|
|
|
Return(IRQP) \
|
|
|
|
|
} \
|
|
|
|
|
\
|
|
|
|
|
Method(_CRS ,0) { \
|
|
|
|
|
CreateWordField(IRQB, 1, IRQN) \
|
|
|
|
|
ShiftLeft(1, pinx, IRQN) \
|
|
|
|
|
Return(IRQB) \
|
|
|
|
|
} \
|
|
|
|
|
\
|
|
|
|
|
Method(_SRS, 1) { \
|
|
|
|
|
CreateWordField(ARG0, 1, IRQM) \
|
|
|
|
|
\
|
|
|
|
|
/* Use lowest available IRQ */ \
|
|
|
|
|
FindSetRightBit(IRQM, Local0) \
|
|
|
|
|
if (Local0) { \
|
|
|
|
|
Decrement(Local0) \
|
|
|
|
|
} \
|
|
|
|
|
Store(Local0, pinx) \
|
|
|
|
|
} \
|
|
|
|
|
} \
|
|
|
|
|
|
|
|
|
|
PCI_INTX_DEV(INTA, PINA, 1)
|
|
|
|
|
PCI_INTX_DEV(INTB, PINB, 2)
|
|
|
|
|
PCI_INTX_DEV(INTC, PINC, 3)
|
|
|
|
|
PCI_INTX_DEV(INTD, PIND, 4)
|
|
|
|
|
}
|
2010-11-24 21:03:09 +01:00
|
|
|
|
|
|
|
|
Field (_SB.PCI0.SBRG.PCIC, ByteAcc, NoLock, Preserve)
|
|
|
|
|
{
|
|
|
|
|
Offset (0x94),
|
|
|
|
|
/* two LSB bits are blink rate */
|
|
|
|
|
LEDR, 2,
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Method (_PTS, 1, NotSerialized)
|
|
|
|
|
{
|
|
|
|
|
/* blink power led while suspended */
|
|
|
|
|
Store (0x1, LEDR)
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Method (_WAK, 1, NotSerialized)
|
|
|
|
|
{
|
|
|
|
|
/* stop power led blinking */
|
|
|
|
|
Store (0x0, LEDR)
|
|
|
|
|
/* wake OK */
|
|
|
|
|
Return(Package(0x02){0x00, 0x00})
|
|
|
|
|
}
|
2010-11-09 23:18:28 +01:00
|
|
|
}
|
