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coreboot-kgpe-d16/src/soc/amd/stoneyridge/finalize.c

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soc/amd: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22fffa0eab006be2bad4d3dd776b22ad9830faef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04 18:50:57 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
amd/stoneyridge: Move TValid and SmmLock to end of POST Delay making TSEG valid until the end of POST. After the CPU setup, there are times where coreboot needs to access the SMRAM from outside of SMM. Also relocate locking of the SMM settings from the CPU init to the end of POST (or just before resuming). Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-24 20:07:11 +01:00
acpi: Move ACPI table support out of arch/x86 (3/5) This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02 19:24:23 +02:00
#include <acpi/acpi.h>
amd/stoneyridge: Move TValid and SmmLock to end of POST Delay making TSEG valid until the end of POST. After the CPU setup, there are times where coreboot needs to access the SMRAM from outside of SMM. Also relocate locking of the SMM settings from the CPU init to the end of POST (or just before resuming). Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-24 20:07:11 +01:00
#include <cpu/x86/mp.h>
#include <cpu/x86/msr.h>
cpu/amd: Use common AMD's MSR Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12 10:54:30 +02:00
#include <cpu/amd/msr.h>
amd/stoneyridge: Move TValid and SmmLock to end of POST Delay making TSEG valid until the end of POST. After the CPU setup, there are times where coreboot needs to access the SMRAM from outside of SMM. Also relocate locking of the SMM settings from the CPU init to the end of POST (or just before resuming). Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-24 20:07:11 +01:00
#include <bootstate.h>
#include <console/console.h>
soc/amd: Move SCI enable outside table creation Preferably, coreboot tables creation is kept hardware-invariant. Change-Id: Id7f79fc959766813d60f847482567579a02db124 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-10-08 18:25:57 +02:00
#include <amdblocks/acpi.h>
amd/stoneyridge: Move TValid and SmmLock to end of POST Delay making TSEG valid until the end of POST. After the CPU setup, there are times where coreboot needs to access the SMRAM from outside of SMM. Also relocate locking of the SMM settings from the CPU init to the end of POST (or just before resuming). Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-24 20:07:11 +01:00
cpu/x86: Add support to run function with argument over APs This patch ensures that user can pass a function with given argument list to execute over APs. BUG=b:74436746 BRANCH=none TEST=Able to run functions over APs with argument. Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-24 10:15:30 +02:00
static void per_core_finalize(void *unused)
amd/stoneyridge: Move TValid and SmmLock to end of POST Delay making TSEG valid until the end of POST. After the CPU setup, there are times where coreboot needs to access the SMRAM from outside of SMM. Also relocate locking of the SMM settings from the CPU init to the end of POST (or just before resuming). Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-24 20:07:11 +01:00
{
msr_t hwcr, mask;
/* Finalize SMM settings */
hwcr = rdmsr(HWCR_MSR);
if (hwcr.lo & SMM_LOCK) /* Skip if already locked, avoid GPF */
return;
soc/amd/stoneyridge,picasso: Switch SMM lock condition SMM_TSEG is a qualifier between TSEG and ASEG memory region. ASEG is deprecated and not supported for this platform in coreboot codebase. The SMM lock should be set based on whether SMM is installed or not, HAVE_SMI_HANDLER currently tells that. Change-Id: I9756f8a59ccfedd59d5b997b35313452dd0c4f46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34127 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08 08:16:13 +02:00
if (CONFIG(HAVE_SMI_HANDLER)) {
cpu/amd: Use common AMD's MSR Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12 10:54:30 +02:00
mask = rdmsr(SMM_MASK_MSR);
amd/stoneyridge: Move TValid and SmmLock to end of POST Delay making TSEG valid until the end of POST. After the CPU setup, there are times where coreboot needs to access the SMRAM from outside of SMM. Also relocate locking of the SMM settings from the CPU init to the end of POST (or just before resuming). Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-24 20:07:11 +01:00
mask.lo |= SMM_TSEG_VALID;
cpu/amd: Use common AMD's MSR Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12 10:54:30 +02:00
wrmsr(SMM_MASK_MSR, mask);
amd/stoneyridge: Move TValid and SmmLock to end of POST Delay making TSEG valid until the end of POST. After the CPU setup, there are times where coreboot needs to access the SMRAM from outside of SMM. Also relocate locking of the SMM settings from the CPU init to the end of POST (or just before resuming). Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-24 20:07:11 +01:00
}
hwcr.lo |= SMM_LOCK;
wrmsr(HWCR_MSR, hwcr);
}
static void finalize_cores(void)
{
int r;
printk(BIOS_SPEW, "Lock SMM configuration\n");
soc/*: mp_run_on_all_cpus: Remove configurable timeout Some timeouts given were too small when serial console is enabled due to its spinlock making code runtime worse with every AP present. In addition we usually don't know how long specific code runs and how long ago it was sent to the APs. Remove the timeout argument from mp_run_on_all_cpus and instead wait up to 1 second, to prevent possible crashing of secondary APs still processing the old job. Tested on Supermicro X11SSH-TF. Change-Id: I456be647b159f7a2ea7d94986a24424e56dcc8c4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-26 14:47:32 +02:00
r = mp_run_on_all_cpus(per_core_finalize, NULL);
amd/stoneyridge: Move TValid and SmmLock to end of POST Delay making TSEG valid until the end of POST. After the CPU setup, there are times where coreboot needs to access the SMRAM from outside of SMM. Also relocate locking of the SMM settings from the CPU init to the end of POST (or just before resuming). Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-24 20:07:11 +01:00
if (r)
printk(BIOS_WARNING, "Failed to finalize all cores\n");
}
static void soc_finalize(void *unused)
{
finalize_cores();
soc/amd: Move SCI enable outside table creation Preferably, coreboot tables creation is kept hardware-invariant. Change-Id: Id7f79fc959766813d60f847482567579a02db124 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-10-08 18:25:57 +02:00
if (!acpi_is_wakeup_s3()) {
if (CONFIG(HAVE_SMI_HANDLER))
acpi_disable_sci();
else
acpi_enable_sci();
}
amd/stoneyridge: Move TValid and SmmLock to end of POST Delay making TSEG valid until the end of POST. After the CPU setup, there are times where coreboot needs to access the SMRAM from outside of SMM. Also relocate locking of the SMM settings from the CPU init to the end of POST (or just before resuming). Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-24 20:07:11 +01:00
post_code(POST_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);
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