2010-08-13 11:18:58 +02:00
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/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2010 Patrick Georgi
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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2011-10-27 13:08:13 +02:00
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//#define USB_DEBUG
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2010-08-13 11:18:58 +02:00
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#include <arch/virtual.h>
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#include <usb/usb.h>
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#include "ohci_private.h"
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#include "ohci.h"
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static void ohci_start (hci_t *controller);
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static void ohci_stop (hci_t *controller);
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static void ohci_reset (hci_t *controller);
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static void ohci_shutdown (hci_t *controller);
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static int ohci_bulk (endpoint_t *ep, int size, u8 *data, int finalize);
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static int ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq,
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int dalen, u8 *data);
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static void* ohci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
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static void ohci_destroy_intr_queue (endpoint_t *ep, void *queue);
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static u8* ohci_poll_intr_queue (void *queue);
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2013-02-21 22:41:40 +01:00
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static int ohci_process_done_queue(ohci_t *ohci, int spew_debug);
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2010-08-13 11:18:58 +02:00
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2013-01-16 12:18:45 +01:00
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#ifdef USB_DEBUG
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2012-12-19 11:10:05 +01:00
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static void
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dump_td (td_t *cur)
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{
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usb_debug("+---------------------------------------------------+\n");
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if (((cur->config & (3UL << 19)) >> 19) == 0)
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usb_debug("|..[SETUP]..........................................|\n");
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else if (((cur->config & (3UL << 8)) >> 8) == 2)
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usb_debug("|..[IN].............................................|\n");
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else if (((cur->config & (3UL << 8)) >> 8) == 1)
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usb_debug("|..[OUT]............................................|\n");
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else
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usb_debug("|..[]...............................................|\n");
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usb_debug("|:|============ OHCI TD at [0x%08lx] ==========|:|\n", virt_to_phys(cur));
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usb_debug("|:| ERRORS = [%ld] | CONFIG = [0x%08lx] | |:|\n",
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3 - ((cur->config & (3UL << 26)) >> 26), cur->config);
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usb_debug("|:+-----------------------------------------------+:|\n");
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usb_debug("|:| C | Condition Code | [%02ld] |:|\n", (cur->config & (0xFUL << 28)) >> 28);
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usb_debug("|:| O | Direction/PID | [%ld] |:|\n", (cur->config & (3UL << 19)) >> 19);
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usb_debug("|:| N | Buffer Rounding | [%ld] |:|\n", (cur->config & (1UL << 18)) >> 18);
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usb_debug("|:| F | Delay Intterrupt | [%ld] |:|\n", (cur->config & (7UL << 21)) >> 21);
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usb_debug("|:| I | Data Toggle | [%ld] |:|\n", (cur->config & (3UL << 24)) >> 24);
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usb_debug("|:| G | Error Count | [%ld] |:|\n", (cur->config & (3UL << 26)) >> 26);
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usb_debug("|:+-----------------------------------------------+:|\n");
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usb_debug("|:| Current Buffer Pointer [0x%08lx] |:|\n", cur->current_buffer_pointer);
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usb_debug("|:+-----------------------------------------------+:|\n");
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usb_debug("|:| Next TD [0x%08lx] |:|\n", cur->next_td);
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usb_debug("|:+-----------------------------------------------+:|\n");
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usb_debug("|:| Current Buffer End [0x%08lx] |:|\n", cur->buffer_end);
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usb_debug("|:|-----------------------------------------------|:|\n");
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usb_debug("|...................................................|\n");
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usb_debug("+---------------------------------------------------+\n");
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}
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static void
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2012-12-19 19:08:45 +01:00
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dump_ed (ed_t *cur)
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2012-12-19 11:10:05 +01:00
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{
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td_t *tmp_td = NULL;
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usb_debug("+===================================================+\n");
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usb_debug("| ############# OHCI ED at [0x%08lx] ########### |\n", virt_to_phys(cur));
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usb_debug("+---------------------------------------------------+\n");
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usb_debug("| Next Endpoint Descriptor [0x%08lx] |\n", cur->next_ed & ~0xFUL);
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usb_debug("+---------------------------------------------------+\n");
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usb_debug("| | @ 0x%08lx : |\n", cur->config);
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usb_debug("| C | Maximum Packet Length | [%04ld] |\n", ((cur->config & (0x3fffUL << 16)) >> 16));
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usb_debug("| O | Function Address | [%04ld] |\n", cur->config & 0x7F);
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usb_debug("| N | Endpoint Number | [%02ld] |\n", (cur->config & (0xFUL << 7)) >> 7);
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usb_debug("| F | Endpoint Direction | [%ld] |\n", ((cur->config & (3UL << 11)) >> 11));
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usb_debug("| I | Endpoint Speed | [%ld] |\n", ((cur->config & (1UL << 13)) >> 13));
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usb_debug("| G | Skip | [%ld] |\n", ((cur->config & (1UL << 14)) >> 14));
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usb_debug("| | Format | [%ld] |\n", ((cur->config & (1UL << 15)) >> 15));
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usb_debug("+---------------------------------------------------+\n");
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usb_debug("| TD Queue Tail Pointer [0x%08lx] |\n", cur->tail_pointer & ~0xFUL);
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usb_debug("+---------------------------------------------------+\n");
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usb_debug("| TD Queue Head Pointer [0x%08lx] |\n", cur->head_pointer & ~0xFUL);
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usb_debug("| CarryToggleBit [%d] Halted [%d] |\n", (u16)(cur->head_pointer & 0x2UL)>>1, (u16)(cur->head_pointer & 0x1UL));
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tmp_td = (td_t *)phys_to_virt((cur->head_pointer & ~0xFUL));
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if ((cur->head_pointer & ~0xFUL) != (cur->tail_pointer & ~0xFUL)) {
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usb_debug("|:::::::::::::::::: OHCI TD CHAIN ::::::::::::::::::|\n");
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while (virt_to_phys(tmp_td) != (cur->tail_pointer & ~0xFUL))
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{
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2012-12-20 09:14:09 +01:00
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dump_td(tmp_td);
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2012-12-19 11:10:05 +01:00
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tmp_td = (td_t *)phys_to_virt((tmp_td->next_td & ~0xFUL));
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}
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usb_debug("|:::::::::::::::: EOF OHCI TD CHAIN ::::::::::::::::|\n");
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usb_debug("+---------------------------------------------------+\n");
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} else {
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usb_debug("+---------------------------------------------------+\n");
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}
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}
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2013-01-16 12:18:45 +01:00
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#endif
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2012-12-19 11:10:05 +01:00
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2010-08-13 11:18:58 +02:00
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static void
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ohci_reset (hci_t *controller)
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{
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2012-07-06 09:54:17 +02:00
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if (controller == NULL)
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return;
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OHCI_INST(controller)->opreg->HcCommandStatus = HostControllerReset;
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mdelay(2); /* wait 2ms */
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2012-07-27 09:51:32 +02:00
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OHCI_INST(controller)->opreg->HcControl = 0;
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2012-07-06 09:54:17 +02:00
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mdelay(10); /* wait 10ms */
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2010-08-13 11:18:58 +02:00
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}
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2012-11-12 16:20:32 +01:00
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static void
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ohci_reinit (hci_t *controller)
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{
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}
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2013-05-03 01:16:41 +02:00
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#if 0 && defined(USB_DEBUG)
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2010-08-13 11:18:58 +02:00
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/* Section 4.3.3 */
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static const char *completion_codes[] = {
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"No error",
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"CRC",
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"Bit stuffing",
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"Data toggle mismatch",
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"Stall",
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"Device not responding",
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"PID check failure",
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"Unexpected PID",
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"Data overrun",
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"Data underrun",
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"--- (10)",
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"--- (11)",
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"Buffer overrun",
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"Buffer underrun",
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"Not accessed (14)",
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"Not accessed (15)"
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};
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/* Section 4.3.1.2 */
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static const char *direction[] = {
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"SETUP",
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"OUT",
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"IN",
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"reserved / from TD"
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};
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#endif
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hci_t *
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2014-07-07 16:33:59 +02:00
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ohci_init (unsigned long physical_bar)
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2010-08-13 11:18:58 +02:00
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{
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int i;
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hci_t *controller = new_controller ();
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2014-04-08 21:54:25 +02:00
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controller->instance = xzalloc(sizeof (ohci_t));
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2017-02-27 18:56:06 +01:00
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controller->reg_base = (uintptr_t)physical_bar;
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2012-06-28 06:30:15 +02:00
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controller->type = OHCI;
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2010-08-13 11:18:58 +02:00
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controller->start = ohci_start;
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controller->stop = ohci_stop;
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controller->reset = ohci_reset;
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2012-11-12 16:20:32 +01:00
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controller->init = ohci_reinit;
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2010-08-13 11:18:58 +02:00
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controller->shutdown = ohci_shutdown;
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controller->bulk = ohci_bulk;
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controller->control = ohci_control;
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2013-05-24 15:48:56 +02:00
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controller->set_address = generic_set_address;
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controller->finish_device_config = NULL;
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controller->destroy_device = NULL;
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2010-08-13 11:18:58 +02:00
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controller->create_intr_queue = ohci_create_intr_queue;
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controller->destroy_intr_queue = ohci_destroy_intr_queue;
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controller->poll_intr_queue = ohci_poll_intr_queue;
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init_device_entry (controller, 0);
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OHCI_INST (controller)->roothub = controller->devices[0];
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2014-07-10 12:56:34 +02:00
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OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(physical_bar);
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2012-12-11 21:08:07 +01:00
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usb_debug("OHCI Version %x.%x\n", (OHCI_INST (controller)->opreg->HcRevision >> 4) & 0xf, OHCI_INST (controller)->opreg->HcRevision & 0xf);
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2010-08-13 11:18:58 +02:00
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if ((OHCI_INST (controller)->opreg->HcControl & HostControllerFunctionalStateMask) == USBReset) {
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/* cold boot */
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OHCI_INST (controller)->opreg->HcControl &= ~RemoteWakeupConnected;
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OHCI_INST (controller)->opreg->HcFmInterval = (11999 * FrameInterval) | ((((11999 - 210)*6)/7) * FSLargestDataPacket);
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/* TODO: right value for PowerOnToPowerGoodTime ? */
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OHCI_INST (controller)->opreg->HcRhDescriptorA = NoPowerSwitching | NoOverCurrentProtection | (10 * PowerOnToPowerGoodTime);
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OHCI_INST (controller)->opreg->HcRhDescriptorB = (0 * DeviceRemovable);
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udelay(100); /* TODO: reset asserting according to USB spec */
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} else if ((OHCI_INST (controller)->opreg->HcControl & HostControllerFunctionalStateMask) != USBOperational) {
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OHCI_INST (controller)->opreg->HcControl = (OHCI_INST (controller)->opreg->HcControl & ~HostControllerFunctionalStateMask) | USBResume;
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udelay(100); /* TODO: resume time according to USB spec */
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}
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int interval = OHCI_INST (controller)->opreg->HcFmInterval;
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OHCI_INST (controller)->opreg->HcCommandStatus = HostControllerReset;
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udelay (10); /* at most 10us for reset to complete. State must be set to Operational within 2ms (5.1.1.4) */
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OHCI_INST (controller)->opreg->HcFmInterval = interval;
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2014-04-08 22:34:11 +02:00
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OHCI_INST (controller)->hcca = dma_memalign(256, 256);
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2019-03-27 18:30:20 +01:00
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if (!OHCI_INST(controller)->hcca)
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fatal("Not enough DMA memory for OHCI HCCA.\n");
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2010-08-13 11:18:58 +02:00
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memset((void*)OHCI_INST (controller)->hcca, 0, 256);
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2014-04-08 22:34:11 +02:00
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if (dma_initialized()) {
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OHCI_INST(controller)->dma_buffer = dma_memalign(4096, DMA_SIZE);
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if (!OHCI_INST(controller)->dma_buffer)
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fatal("Not enough DMA memory for OHCI bounce buffer.\n");
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}
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2012-06-20 11:37:17 +02:00
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/* Initialize interrupt table. */
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u32 *const intr_table = OHCI_INST(controller)->hcca->HccaInterruptTable;
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2014-04-08 22:34:11 +02:00
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ed_t *const periodic_ed = dma_memalign(sizeof(ed_t), sizeof(ed_t));
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2019-03-27 18:30:20 +01:00
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if (!periodic_ed)
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fatal("Not enough DMA memory for OHCI interrupt table.\n");
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2012-06-20 11:37:17 +02:00
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memset((void *)periodic_ed, 0, sizeof(*periodic_ed));
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for (i = 0; i < 32; ++i)
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intr_table[i] = virt_to_phys(periodic_ed);
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OHCI_INST (controller)->periodic_ed = periodic_ed;
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2010-08-13 11:18:58 +02:00
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OHCI_INST (controller)->opreg->HcHCCA = virt_to_phys(OHCI_INST (controller)->hcca);
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2012-06-20 14:58:21 +02:00
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/* Make sure periodic schedule is enabled. */
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OHCI_INST (controller)->opreg->HcControl |= PeriodicListEnable;
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2010-08-13 11:18:58 +02:00
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OHCI_INST (controller)->opreg->HcControl &= ~IsochronousEnable; // unused by this driver
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// disable everything, contrary to what OHCI spec says in 5.1.1.4, as we don't need IRQs
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2017-06-27 21:51:20 +02:00
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OHCI_INST (controller)->opreg->HcInterruptEnable = 1 << 31;
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OHCI_INST (controller)->opreg->HcInterruptDisable = ~(1 << 31);
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2010-08-13 11:18:58 +02:00
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OHCI_INST (controller)->opreg->HcInterruptStatus = ~0;
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OHCI_INST (controller)->opreg->HcPeriodicStart = (((OHCI_INST (controller)->opreg->HcFmInterval & FrameIntervalMask) / 10) * 9);
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OHCI_INST (controller)->opreg->HcControl = (OHCI_INST (controller)->opreg->HcControl & ~HostControllerFunctionalStateMask) | USBOperational;
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mdelay(100);
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controller->devices[0]->controller = controller;
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controller->devices[0]->init = ohci_rh_init;
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controller->devices[0]->init (controller->devices[0]);
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return controller;
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}
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|
2019-03-06 01:55:15 +01:00
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#if CONFIG(LP_USB_PCI)
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2013-05-03 01:16:41 +02:00
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hci_t *
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ohci_pci_init (pcidev_t addr)
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{
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u32 reg_base;
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/* regarding OHCI spec, Appendix A, BAR_OHCI register description, Table A-4
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* BASE ADDRESS only [31-12] bits. All other usually 0, but not all.
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* OHCI mandates MMIO, so bit 0 is clear */
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reg_base = pci_read_config32 (addr, 0x10) & 0xfffff000;
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2014-07-07 16:33:59 +02:00
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return ohci_init((unsigned long)reg_base);
|
2013-05-03 01:16:41 +02:00
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}
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#endif
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|
2010-08-13 11:18:58 +02:00
|
|
|
static void
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ohci_shutdown (hci_t *controller)
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|
|
{
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|
if (controller == 0)
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return;
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|
|
detach_controller (controller);
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|
|
ohci_stop(controller);
|
2016-12-23 06:52:07 +01:00
|
|
|
ohci_reset(controller);
|
2014-04-08 21:54:25 +02:00
|
|
|
free (OHCI_INST (controller)->hcca);
|
2012-06-20 11:37:17 +02:00
|
|
|
free ((void *)OHCI_INST (controller)->periodic_ed);
|
2010-08-13 11:18:58 +02:00
|
|
|
free (OHCI_INST (controller));
|
|
|
|
free (controller);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
ohci_start (hci_t *controller)
|
|
|
|
{
|
2014-04-08 21:54:25 +02:00
|
|
|
OHCI_INST (controller)->opreg->HcControl |= PeriodicListEnable;
|
2010-08-13 11:18:58 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
ohci_stop (hci_t *controller)
|
|
|
|
{
|
2014-04-08 21:54:25 +02:00
|
|
|
OHCI_INST (controller)->opreg->HcControl &= ~PeriodicListEnable;
|
2010-08-13 11:18:58 +02:00
|
|
|
}
|
|
|
|
|
2019-06-22 00:39:59 +02:00
|
|
|
#define OHCI_SLEEP_TIME_US 1000
|
|
|
|
|
2010-08-13 11:18:58 +02:00
|
|
|
static int
|
2012-05-21 14:46:26 +02:00
|
|
|
wait_for_ed(usbdev_t *dev, ed_t *head, int pages)
|
2010-08-13 11:18:58 +02:00
|
|
|
{
|
|
|
|
/* wait for results */
|
2019-06-22 00:39:59 +02:00
|
|
|
int timeout = USB_MAX_PROCESSING_TIME_US / OHCI_SLEEP_TIME_US;
|
2010-08-13 11:18:58 +02:00
|
|
|
while (((head->head_pointer & ~3) != head->tail_pointer) &&
|
|
|
|
!(head->head_pointer & 1) &&
|
2012-05-21 14:46:26 +02:00
|
|
|
((((td_t*)phys_to_virt(head->head_pointer & ~3))->config
|
|
|
|
& TD_CC_MASK) >= TD_CC_NOACCESS) &&
|
|
|
|
timeout--) {
|
|
|
|
/* don't log every ms */
|
|
|
|
if (!(timeout % 100))
|
2012-11-01 23:44:10 +01:00
|
|
|
usb_debug("intst: %x; ctrl: %x; cmdst: %x; head: %x -> %x, tail: %x, condition: %x\n",
|
2010-08-13 11:18:58 +02:00
|
|
|
OHCI_INST(dev->controller)->opreg->HcInterruptStatus,
|
|
|
|
OHCI_INST(dev->controller)->opreg->HcControl,
|
|
|
|
OHCI_INST(dev->controller)->opreg->HcCommandStatus,
|
|
|
|
head->head_pointer,
|
|
|
|
((td_t*)phys_to_virt(head->head_pointer & ~3))->next_td,
|
|
|
|
head->tail_pointer,
|
2011-11-24 09:12:11 +01:00
|
|
|
(((td_t*)phys_to_virt(head->head_pointer & ~3))->config & TD_CC_MASK) >> TD_CC_SHIFT);
|
2019-06-22 00:39:59 +02:00
|
|
|
udelay(OHCI_SLEEP_TIME_US);
|
2010-08-13 11:18:58 +02:00
|
|
|
}
|
2019-06-22 00:39:59 +02:00
|
|
|
if (timeout <= 0)
|
2012-12-11 21:08:07 +01:00
|
|
|
usb_debug("Error: ohci: endpoint "
|
2012-05-21 14:46:26 +02:00
|
|
|
"descriptor processing timed out.\n");
|
2012-06-20 10:08:06 +02:00
|
|
|
/* Clear the done queue. */
|
2013-02-21 22:41:40 +01:00
|
|
|
int result = ohci_process_done_queue(OHCI_INST(dev->controller), 1);
|
2010-08-13 11:18:58 +02:00
|
|
|
|
|
|
|
if (head->head_pointer & 1) {
|
2012-11-01 23:44:10 +01:00
|
|
|
usb_debug("HALTED!\n");
|
2013-02-21 22:41:40 +01:00
|
|
|
return -1;
|
2010-08-13 11:18:58 +02:00
|
|
|
}
|
2013-02-21 22:41:40 +01:00
|
|
|
return result;
|
2010-08-13 11:18:58 +02:00
|
|
|
}
|
|
|
|
|
2012-06-20 10:08:06 +02:00
|
|
|
static void
|
|
|
|
ohci_free_ed (ed_t *const head)
|
|
|
|
{
|
|
|
|
/* In case the transfer canceled, we have to free unprocessed TDs. */
|
|
|
|
while ((head->head_pointer & ~0x3) != head->tail_pointer) {
|
|
|
|
/* Save current TD pointer. */
|
|
|
|
td_t *const cur_td =
|
|
|
|
(td_t*)phys_to_virt(head->head_pointer & ~0x3);
|
|
|
|
/* Advance head pointer. */
|
|
|
|
head->head_pointer = cur_td->next_td;
|
|
|
|
/* Free current TD. */
|
|
|
|
free((void *)cur_td);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Always free the dummy TD */
|
|
|
|
if ((head->head_pointer & ~0x3) == head->tail_pointer)
|
|
|
|
free(phys_to_virt(head->head_pointer & ~0x3));
|
|
|
|
/* and the ED. */
|
|
|
|
free((void *)head);
|
|
|
|
}
|
|
|
|
|
2010-08-13 11:18:58 +02:00
|
|
|
static int
|
2014-04-08 22:34:11 +02:00
|
|
|
ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen,
|
|
|
|
unsigned char *src)
|
2010-08-13 11:18:58 +02:00
|
|
|
{
|
2014-04-08 22:34:11 +02:00
|
|
|
u8 *data = src;
|
|
|
|
u8 *devreq = setup;
|
2013-02-21 22:41:40 +01:00
|
|
|
int remaining = dalen;
|
2010-08-13 11:18:58 +02:00
|
|
|
td_t *cur;
|
|
|
|
|
2014-04-08 22:34:11 +02:00
|
|
|
if (!dma_coherent(devreq)) {
|
|
|
|
devreq = OHCI_INST(dev->controller)->dma_buffer;
|
|
|
|
memcpy(devreq, setup, drlen);
|
|
|
|
}
|
|
|
|
if (dalen > 0 && !dma_coherent(src)) {
|
|
|
|
data = OHCI_INST(dev->controller)->dma_buffer + drlen;
|
|
|
|
if (drlen + dalen > DMA_SIZE) {
|
|
|
|
usb_debug("OHCI control transfer too large for DMA buffer: %d\n", drlen + dalen);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
if (dir == OUT)
|
|
|
|
memcpy(data, src, dalen);
|
|
|
|
}
|
|
|
|
|
2010-08-13 11:18:58 +02:00
|
|
|
// pages are specified as 4K in OHCI, so don't use getpagesize()
|
|
|
|
int first_page = (unsigned long)data / 4096;
|
|
|
|
int last_page = (unsigned long)(data+dalen-1)/4096;
|
|
|
|
if (last_page < first_page) last_page = first_page;
|
2018-04-26 10:11:10 +02:00
|
|
|
int pages = (dalen == 0)?0:(last_page - first_page + 1);
|
2010-08-13 11:18:58 +02:00
|
|
|
|
2012-06-20 10:08:06 +02:00
|
|
|
/* First TD. */
|
2014-04-08 22:34:11 +02:00
|
|
|
td_t *const first_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
|
2019-03-27 18:30:20 +01:00
|
|
|
if (!first_td)
|
|
|
|
fatal("Not enough DMA memory for OHCI first TD in buffer.\n");
|
2012-06-20 10:08:06 +02:00
|
|
|
memset((void *)first_td, 0, sizeof(*first_td));
|
|
|
|
cur = first_td;
|
2010-08-13 11:18:58 +02:00
|
|
|
|
2012-06-20 10:08:06 +02:00
|
|
|
cur->config = TD_DIRECTION_SETUP |
|
|
|
|
TD_DELAY_INTERRUPT_NOINTR |
|
2011-11-24 09:12:11 +01:00
|
|
|
TD_TOGGLE_FROM_TD |
|
|
|
|
TD_TOGGLE_DATA0 |
|
|
|
|
TD_CC_NOACCESS;
|
2012-06-20 10:08:06 +02:00
|
|
|
cur->current_buffer_pointer = virt_to_phys(devreq);
|
|
|
|
cur->buffer_end = virt_to_phys(devreq + drlen - 1);
|
2010-08-13 11:18:58 +02:00
|
|
|
|
|
|
|
while (pages > 0) {
|
2012-06-20 10:08:06 +02:00
|
|
|
/* One more TD. */
|
2014-04-08 22:34:11 +02:00
|
|
|
td_t *const next = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
|
2019-03-27 18:30:20 +01:00
|
|
|
if (!next)
|
|
|
|
fatal("Not enough DMA memory for OHCI new page.\n");
|
2012-06-20 10:08:06 +02:00
|
|
|
memset((void *)next, 0, sizeof(*next));
|
|
|
|
/* Linked to the previous. */
|
|
|
|
cur->next_td = virt_to_phys(next);
|
|
|
|
/* Advance to the new TD. */
|
|
|
|
cur = next;
|
|
|
|
|
2012-05-29 14:28:26 +02:00
|
|
|
cur->config = (dir == IN ? TD_DIRECTION_IN : TD_DIRECTION_OUT) |
|
2012-06-20 10:08:06 +02:00
|
|
|
TD_DELAY_INTERRUPT_NOINTR |
|
2011-11-24 09:12:11 +01:00
|
|
|
TD_TOGGLE_FROM_ED |
|
|
|
|
TD_CC_NOACCESS;
|
2010-08-13 11:18:58 +02:00
|
|
|
cur->current_buffer_pointer = virt_to_phys(data);
|
|
|
|
pages--;
|
|
|
|
int consumed = (4096 - ((unsigned long)data % 4096));
|
2013-02-21 22:41:40 +01:00
|
|
|
if (consumed >= remaining) {
|
2010-08-13 11:18:58 +02:00
|
|
|
// end of data is within same page
|
2013-02-21 22:41:40 +01:00
|
|
|
cur->buffer_end = virt_to_phys(data + remaining - 1);
|
|
|
|
remaining = 0;
|
2010-08-13 11:18:58 +02:00
|
|
|
/* assert(pages == 0); */
|
|
|
|
} else {
|
2013-02-21 22:41:40 +01:00
|
|
|
remaining -= consumed;
|
2010-08-13 11:18:58 +02:00
|
|
|
data += consumed;
|
|
|
|
pages--;
|
2013-02-21 22:41:40 +01:00
|
|
|
int second_page_size = remaining;
|
|
|
|
if (remaining > 4096) {
|
2010-08-13 11:18:58 +02:00
|
|
|
second_page_size = 4096;
|
|
|
|
}
|
|
|
|
cur->buffer_end = virt_to_phys(data + second_page_size - 1);
|
2013-02-21 22:41:40 +01:00
|
|
|
remaining -= second_page_size;
|
2010-08-13 11:18:58 +02:00
|
|
|
data += second_page_size;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-06-20 10:08:06 +02:00
|
|
|
/* One more TD. */
|
2014-04-08 22:34:11 +02:00
|
|
|
td_t *const next_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
|
2019-03-27 18:30:20 +01:00
|
|
|
if (!next_td)
|
|
|
|
fatal("Not enough DMA memory for OHCI additional TD.\n");
|
2012-06-20 10:08:06 +02:00
|
|
|
memset((void *)next_td, 0, sizeof(*next_td));
|
|
|
|
/* Linked to the previous. */
|
|
|
|
cur->next_td = virt_to_phys(next_td);
|
|
|
|
/* Advance to the new TD. */
|
|
|
|
cur = next_td;
|
2012-05-29 14:28:26 +02:00
|
|
|
cur->config = (dir == IN ? TD_DIRECTION_OUT : TD_DIRECTION_IN) |
|
2012-06-20 10:08:06 +02:00
|
|
|
TD_DELAY_INTERRUPT_ZERO | /* Write done head after this TD. */
|
2011-11-24 09:12:11 +01:00
|
|
|
TD_TOGGLE_FROM_TD |
|
|
|
|
TD_TOGGLE_DATA1 |
|
|
|
|
TD_CC_NOACCESS;
|
2010-08-13 11:18:58 +02:00
|
|
|
cur->current_buffer_pointer = 0;
|
|
|
|
cur->buffer_end = 0;
|
|
|
|
|
2012-06-20 10:08:06 +02:00
|
|
|
/* Final dummy TD. */
|
2014-04-08 22:34:11 +02:00
|
|
|
td_t *const final_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
|
2019-03-27 18:30:20 +01:00
|
|
|
if (!final_td)
|
|
|
|
fatal("Not enough DMA memory for OHCI dummy TD!\n");
|
2012-06-20 10:08:06 +02:00
|
|
|
memset((void *)final_td, 0, sizeof(*final_td));
|
|
|
|
/* Linked to the previous. */
|
|
|
|
cur->next_td = virt_to_phys(final_td);
|
2010-08-13 11:18:58 +02:00
|
|
|
|
|
|
|
/* Data structures */
|
2014-04-08 22:34:11 +02:00
|
|
|
ed_t *head = dma_memalign(sizeof(ed_t), sizeof(ed_t));
|
2019-03-27 18:30:20 +01:00
|
|
|
if (!head)
|
|
|
|
fatal("Not enough DMA memory for OHCI data structures.\n");
|
2010-08-13 11:18:58 +02:00
|
|
|
memset((void*)head, 0, sizeof(*head));
|
2011-11-24 09:12:11 +01:00
|
|
|
head->config = (dev->address << ED_FUNC_SHIFT) |
|
|
|
|
(0 << ED_EP_SHIFT) |
|
|
|
|
(OHCI_FROM_TD << ED_DIR_SHIFT) |
|
|
|
|
(dev->speed?ED_LOWSPEED:0) |
|
|
|
|
(dev->endpoints[0].maxpacketsize << ED_MPS_SHIFT);
|
2012-06-20 10:08:06 +02:00
|
|
|
head->tail_pointer = virt_to_phys(final_td);
|
|
|
|
head->head_pointer = virt_to_phys(first_td);
|
2010-08-13 11:18:58 +02:00
|
|
|
|
2012-12-19 11:10:05 +01:00
|
|
|
usb_debug("ohci_control(): doing transfer with %x. first_td at %x\n",
|
2012-06-20 10:08:06 +02:00
|
|
|
head->config & ED_FUNC_MASK, virt_to_phys(first_td));
|
2013-01-16 12:18:45 +01:00
|
|
|
#ifdef USB_DEBUG
|
2012-12-19 11:10:05 +01:00
|
|
|
dump_ed(head);
|
|
|
|
#endif
|
2010-08-13 11:18:58 +02:00
|
|
|
|
|
|
|
/* activate schedule */
|
|
|
|
OHCI_INST(dev->controller)->opreg->HcControlHeadED = virt_to_phys(head);
|
2011-10-27 13:08:13 +02:00
|
|
|
OHCI_INST(dev->controller)->opreg->HcControl |= ControlListEnable;
|
2010-08-13 11:18:58 +02:00
|
|
|
OHCI_INST(dev->controller)->opreg->HcCommandStatus = ControlListFilled;
|
|
|
|
|
2013-02-21 22:41:40 +01:00
|
|
|
int result = wait_for_ed(dev, head,
|
2018-04-26 10:11:10 +02:00
|
|
|
(dalen == 0)?0:(last_page - first_page + 1));
|
2012-06-19 10:27:00 +02:00
|
|
|
/* Wait some frames before and one after disabling list access. */
|
|
|
|
mdelay(4);
|
2011-10-27 13:08:13 +02:00
|
|
|
OHCI_INST(dev->controller)->opreg->HcControl &= ~ControlListEnable;
|
2012-06-19 10:27:00 +02:00
|
|
|
mdelay(1);
|
2010-08-13 11:18:58 +02:00
|
|
|
|
|
|
|
/* free memory */
|
2012-06-20 10:08:06 +02:00
|
|
|
ohci_free_ed(head);
|
2010-08-13 11:18:58 +02:00
|
|
|
|
2014-04-08 22:34:11 +02:00
|
|
|
if (result >= 0) {
|
2013-02-21 22:41:40 +01:00
|
|
|
result = dalen - result;
|
2014-04-08 22:34:11 +02:00
|
|
|
if (dir == IN && data != src)
|
|
|
|
memcpy(src, data, result);
|
|
|
|
}
|
2013-02-21 22:41:40 +01:00
|
|
|
|
|
|
|
return result;
|
2010-08-13 11:18:58 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* finalize == 1: if data is of packet aligned size, add a zero length packet */
|
|
|
|
static int
|
2014-04-08 22:34:11 +02:00
|
|
|
ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize)
|
2010-08-13 11:18:58 +02:00
|
|
|
{
|
|
|
|
int i;
|
2012-06-20 10:08:06 +02:00
|
|
|
td_t *cur, *next;
|
2014-04-08 22:34:11 +02:00
|
|
|
int remaining = dalen;
|
|
|
|
u8 *data = src;
|
|
|
|
usb_debug("bulk: %x bytes from %x, finalize: %x, maxpacketsize: %x\n", dalen, src, finalize, ep->maxpacketsize);
|
|
|
|
|
|
|
|
if (!dma_coherent(src)) {
|
|
|
|
data = OHCI_INST(ep->dev->controller)->dma_buffer;
|
|
|
|
if (dalen > DMA_SIZE) {
|
|
|
|
usb_debug("OHCI bulk transfer too large for DMA buffer: %d\n", dalen);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
if (ep->direction == OUT)
|
|
|
|
memcpy(data, src, dalen);
|
|
|
|
}
|
2010-08-13 11:18:58 +02:00
|
|
|
|
|
|
|
// pages are specified as 4K in OHCI, so don't use getpagesize()
|
|
|
|
int first_page = (unsigned long)data / 4096;
|
|
|
|
int last_page = (unsigned long)(data+dalen-1)/4096;
|
|
|
|
if (last_page < first_page) last_page = first_page;
|
2018-04-26 10:11:10 +02:00
|
|
|
int pages = (dalen == 0)?0:(last_page - first_page + 1);
|
2010-08-13 11:18:58 +02:00
|
|
|
int td_count = (pages+1)/2;
|
|
|
|
|
|
|
|
if (finalize && ((dalen % ep->maxpacketsize) == 0)) {
|
|
|
|
td_count++;
|
|
|
|
}
|
|
|
|
|
2012-06-20 10:08:06 +02:00
|
|
|
/* First TD. */
|
2014-04-08 22:34:11 +02:00
|
|
|
td_t *const first_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
|
2019-03-27 18:30:20 +01:00
|
|
|
if (!first_td)
|
|
|
|
fatal("Not enough DMA memory for OHCI bulk transfer.\n");
|
2012-06-20 10:08:06 +02:00
|
|
|
memset((void *)first_td, 0, sizeof(*first_td));
|
|
|
|
cur = next = first_td;
|
2010-08-13 11:18:58 +02:00
|
|
|
|
2012-06-20 10:08:06 +02:00
|
|
|
for (i = 0; i < td_count; ++i) {
|
|
|
|
/* Advance to next TD. */
|
|
|
|
cur = next;
|
2012-05-29 14:28:26 +02:00
|
|
|
cur->config = (ep->direction == IN ? TD_DIRECTION_IN : TD_DIRECTION_OUT) |
|
2012-06-20 10:08:06 +02:00
|
|
|
TD_DELAY_INTERRUPT_NOINTR |
|
2011-11-24 09:12:11 +01:00
|
|
|
TD_TOGGLE_FROM_ED |
|
|
|
|
TD_CC_NOACCESS;
|
2011-10-21 15:45:09 +02:00
|
|
|
cur->current_buffer_pointer = virt_to_phys(data);
|
2010-08-13 11:18:58 +02:00
|
|
|
pages--;
|
2013-02-21 22:41:40 +01:00
|
|
|
if (remaining == 0) {
|
2010-08-13 11:18:58 +02:00
|
|
|
/* magic TD for empty packet transfer */
|
|
|
|
cur->current_buffer_pointer = 0;
|
|
|
|
cur->buffer_end = 0;
|
|
|
|
/* assert((pages == 0) && finalize); */
|
|
|
|
}
|
|
|
|
int consumed = (4096 - ((unsigned long)data % 4096));
|
2013-02-21 22:41:40 +01:00
|
|
|
if (consumed >= remaining) {
|
2010-08-13 11:18:58 +02:00
|
|
|
// end of data is within same page
|
2013-02-21 22:41:40 +01:00
|
|
|
cur->buffer_end = virt_to_phys(data + remaining - 1);
|
|
|
|
remaining = 0;
|
2010-08-13 11:18:58 +02:00
|
|
|
/* assert(pages == finalize); */
|
|
|
|
} else {
|
2013-02-21 22:41:40 +01:00
|
|
|
remaining -= consumed;
|
2010-08-13 11:18:58 +02:00
|
|
|
data += consumed;
|
|
|
|
pages--;
|
2013-02-21 22:41:40 +01:00
|
|
|
int second_page_size = remaining;
|
|
|
|
if (remaining > 4096) {
|
2010-08-13 11:18:58 +02:00
|
|
|
second_page_size = 4096;
|
|
|
|
}
|
|
|
|
cur->buffer_end = virt_to_phys(data + second_page_size - 1);
|
2013-02-21 22:41:40 +01:00
|
|
|
remaining -= second_page_size;
|
2010-08-13 11:18:58 +02:00
|
|
|
data += second_page_size;
|
|
|
|
}
|
2012-06-20 10:08:06 +02:00
|
|
|
/* One more TD. */
|
2014-04-08 22:34:11 +02:00
|
|
|
next = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
|
2019-03-27 18:30:20 +01:00
|
|
|
if (!next)
|
|
|
|
fatal("Not enough DMA mem for TD bulk transfer.\n");
|
2012-06-20 10:08:06 +02:00
|
|
|
memset((void *)next, 0, sizeof(*next));
|
|
|
|
/* Linked to the previous. */
|
|
|
|
cur->next_td = virt_to_phys(next);
|
2010-08-13 11:18:58 +02:00
|
|
|
}
|
|
|
|
|
2012-06-20 10:08:06 +02:00
|
|
|
/* Write done head after last TD. */
|
|
|
|
cur->config &= ~TD_DELAY_INTERRUPT_MASK;
|
|
|
|
/* Advance to final, dummy TD. */
|
|
|
|
cur = next;
|
|
|
|
|
2010-08-13 11:18:58 +02:00
|
|
|
/* Data structures */
|
2014-04-08 22:34:11 +02:00
|
|
|
ed_t *head = dma_memalign(sizeof(ed_t), sizeof(ed_t));
|
2019-03-27 18:30:20 +01:00
|
|
|
if (!head)
|
|
|
|
fatal("Not enough DMA memory for OHCI bulk transfer's head.\n");
|
2010-08-13 11:18:58 +02:00
|
|
|
memset((void*)head, 0, sizeof(*head));
|
2011-11-24 09:12:11 +01:00
|
|
|
head->config = (ep->dev->address << ED_FUNC_SHIFT) |
|
|
|
|
((ep->endpoint & 0xf) << ED_EP_SHIFT) |
|
2018-04-26 10:11:10 +02:00
|
|
|
(((ep->direction == IN)?OHCI_IN:OHCI_OUT) << ED_DIR_SHIFT) |
|
2011-11-24 09:12:11 +01:00
|
|
|
(ep->dev->speed?ED_LOWSPEED:0) |
|
|
|
|
(ep->maxpacketsize << ED_MPS_SHIFT);
|
2010-08-13 11:18:58 +02:00
|
|
|
head->tail_pointer = virt_to_phys(cur);
|
2012-06-20 10:08:06 +02:00
|
|
|
head->head_pointer = virt_to_phys(first_td) | (ep->toggle?ED_TOGGLE:0);
|
2010-08-13 11:18:58 +02:00
|
|
|
|
2012-11-01 23:44:10 +01:00
|
|
|
usb_debug("doing bulk transfer with %x(%x). first_td at %x, last %x\n",
|
2012-06-20 10:08:06 +02:00
|
|
|
head->config & ED_FUNC_MASK,
|
|
|
|
(head->config & ED_EP_MASK) >> ED_EP_SHIFT,
|
|
|
|
virt_to_phys(first_td), virt_to_phys(cur));
|
2010-08-13 11:18:58 +02:00
|
|
|
|
|
|
|
/* activate schedule */
|
|
|
|
OHCI_INST(ep->dev->controller)->opreg->HcBulkHeadED = virt_to_phys(head);
|
2011-10-27 13:08:13 +02:00
|
|
|
OHCI_INST(ep->dev->controller)->opreg->HcControl |= BulkListEnable;
|
2010-08-13 11:18:58 +02:00
|
|
|
OHCI_INST(ep->dev->controller)->opreg->HcCommandStatus = BulkListFilled;
|
|
|
|
|
2013-02-21 22:41:40 +01:00
|
|
|
int result = wait_for_ed(ep->dev, head,
|
2018-04-26 10:11:10 +02:00
|
|
|
(dalen == 0)?0:(last_page - first_page + 1));
|
2012-06-19 10:27:00 +02:00
|
|
|
/* Wait some frames before and one after disabling list access. */
|
|
|
|
mdelay(4);
|
2011-10-27 13:08:13 +02:00
|
|
|
OHCI_INST(ep->dev->controller)->opreg->HcControl &= ~BulkListEnable;
|
2012-06-19 10:27:00 +02:00
|
|
|
mdelay(1);
|
2010-08-13 11:18:58 +02:00
|
|
|
|
2011-11-24 09:12:11 +01:00
|
|
|
ep->toggle = head->head_pointer & ED_TOGGLE;
|
2010-08-13 11:18:58 +02:00
|
|
|
|
|
|
|
/* free memory */
|
2012-06-20 10:08:06 +02:00
|
|
|
ohci_free_ed(head);
|
2010-08-13 11:18:58 +02:00
|
|
|
|
2014-04-08 22:34:11 +02:00
|
|
|
if (result >= 0) {
|
2013-02-21 22:41:40 +01:00
|
|
|
result = dalen - result;
|
2014-04-08 22:34:11 +02:00
|
|
|
if (ep->direction == IN && data != src)
|
|
|
|
memcpy(src, data, result);
|
2014-04-08 22:37:39 +02:00
|
|
|
}
|
2010-08-13 11:18:58 +02:00
|
|
|
|
2013-02-21 22:41:40 +01:00
|
|
|
return result;
|
2010-08-13 11:18:58 +02:00
|
|
|
}
|
|
|
|
|
2012-06-20 14:58:21 +02:00
|
|
|
|
|
|
|
struct _intr_queue;
|
|
|
|
|
|
|
|
struct _intrq_td {
|
|
|
|
volatile td_t td;
|
|
|
|
u8 *data;
|
|
|
|
struct _intrq_td *next;
|
|
|
|
struct _intr_queue *intrq;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct _intr_queue {
|
|
|
|
volatile ed_t ed;
|
|
|
|
struct _intrq_td *head;
|
|
|
|
struct _intrq_td *tail;
|
|
|
|
u8 *data;
|
|
|
|
int reqsize;
|
|
|
|
endpoint_t *endp;
|
|
|
|
unsigned int remaining_tds;
|
2012-11-22 17:21:57 +01:00
|
|
|
int destroy;
|
2012-06-20 14:58:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
typedef struct _intrq_td intrq_td_t;
|
|
|
|
typedef struct _intr_queue intr_queue_t;
|
|
|
|
|
|
|
|
#define INTRQ_TD_FROM_TD(x) ((intrq_td_t *)x)
|
|
|
|
|
|
|
|
static void
|
|
|
|
ohci_fill_intrq_td(intrq_td_t *const td, intr_queue_t *const intrq,
|
|
|
|
u8 *const data)
|
|
|
|
{
|
|
|
|
memset(td, 0, sizeof(*td));
|
|
|
|
td->td.config = TD_QUEUETYPE_INTR |
|
|
|
|
(intrq->endp->direction == IN
|
|
|
|
? TD_DIRECTION_IN : TD_DIRECTION_OUT) |
|
|
|
|
TD_DELAY_INTERRUPT_ZERO |
|
|
|
|
TD_TOGGLE_FROM_ED |
|
|
|
|
TD_CC_NOACCESS;
|
|
|
|
td->td.current_buffer_pointer = virt_to_phys(data);
|
|
|
|
td->td.buffer_end = td->td.current_buffer_pointer + intrq->reqsize - 1;
|
|
|
|
td->intrq = intrq;
|
|
|
|
td->data = data;
|
|
|
|
}
|
|
|
|
|
2010-08-13 11:18:58 +02:00
|
|
|
/* create and hook-up an intr queue into device schedule */
|
2012-06-20 14:58:21 +02:00
|
|
|
static void *
|
|
|
|
ohci_create_intr_queue(endpoint_t *const ep, const int reqsize,
|
|
|
|
const int reqcount, const int reqtiming)
|
2010-08-13 11:18:58 +02:00
|
|
|
{
|
2012-06-20 14:58:21 +02:00
|
|
|
int i;
|
|
|
|
intrq_td_t *first_td = NULL, *last_td = NULL;
|
|
|
|
|
|
|
|
if (reqsize > 4096)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
intr_queue_t *const intrq =
|
2014-04-08 22:34:11 +02:00
|
|
|
(intr_queue_t *)dma_memalign(sizeof(intrq->ed), sizeof(*intrq));
|
2019-03-27 18:30:20 +01:00
|
|
|
if (!intrq) {
|
|
|
|
usb_debug("Not enough DMA memory for intr queue.\n");
|
|
|
|
free(intrq);
|
|
|
|
return NULL;
|
|
|
|
}
|
2012-06-20 14:58:21 +02:00
|
|
|
memset(intrq, 0, sizeof(*intrq));
|
2014-04-08 22:34:11 +02:00
|
|
|
intrq->data = (u8 *)dma_malloc(reqcount * reqsize);
|
2012-06-20 14:58:21 +02:00
|
|
|
intrq->reqsize = reqsize;
|
|
|
|
intrq->endp = ep;
|
|
|
|
|
|
|
|
/* Create #reqcount TDs. */
|
|
|
|
u8 *cur_data = intrq->data;
|
|
|
|
for (i = 0; i < reqcount; ++i) {
|
2014-04-08 22:34:11 +02:00
|
|
|
intrq_td_t *const td = dma_memalign(sizeof(td->td), sizeof(*td));
|
2019-03-27 18:30:20 +01:00
|
|
|
if (!td)
|
|
|
|
fatal("Not enough DMA mem to transfer descriptor.\n");
|
2012-06-20 14:58:21 +02:00
|
|
|
++intrq->remaining_tds;
|
|
|
|
ohci_fill_intrq_td(td, intrq, cur_data);
|
|
|
|
cur_data += reqsize;
|
|
|
|
if (!first_td)
|
|
|
|
first_td = td;
|
|
|
|
else
|
|
|
|
last_td->td.next_td = virt_to_phys(&td->td);
|
|
|
|
last_td = td;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Create last, dummy TD. */
|
2014-04-08 22:34:11 +02:00
|
|
|
intrq_td_t *dummy_td = dma_memalign(sizeof(dummy_td->td), sizeof(*dummy_td));
|
2019-03-27 18:30:20 +01:00
|
|
|
if (!dummy_td)
|
|
|
|
fatal("Not enough memory to add dummy TD.\n");
|
2012-06-20 14:58:21 +02:00
|
|
|
memset(dummy_td, 0, sizeof(*dummy_td));
|
|
|
|
dummy_td->intrq = intrq;
|
|
|
|
if (last_td)
|
|
|
|
last_td->td.next_td = virt_to_phys(&dummy_td->td);
|
|
|
|
last_td = dummy_td;
|
|
|
|
|
|
|
|
/* Initialize ED. */
|
|
|
|
intrq->ed.config = (ep->dev->address << ED_FUNC_SHIFT) |
|
|
|
|
((ep->endpoint & 0xf) << ED_EP_SHIFT) |
|
|
|
|
(((ep->direction == IN) ? OHCI_IN : OHCI_OUT) << ED_DIR_SHIFT) |
|
|
|
|
(ep->dev->speed ? ED_LOWSPEED : 0) |
|
|
|
|
(ep->maxpacketsize << ED_MPS_SHIFT);
|
|
|
|
intrq->ed.tail_pointer = virt_to_phys(last_td);
|
|
|
|
intrq->ed.head_pointer = virt_to_phys(first_td) |
|
|
|
|
(ep->toggle ? ED_TOGGLE : 0);
|
|
|
|
|
|
|
|
/* Insert ED into periodic table. */
|
|
|
|
int nothing_placed = 1;
|
|
|
|
ohci_t *const ohci = OHCI_INST(ep->dev->controller);
|
|
|
|
u32 *const intr_table = ohci->hcca->HccaInterruptTable;
|
|
|
|
const u32 dummy_ptr = virt_to_phys(ohci->periodic_ed);
|
|
|
|
for (i = 0; i < 32; i += reqtiming) {
|
|
|
|
/* Advance to the next free position. */
|
|
|
|
while ((i < 32) && (intr_table[i] != dummy_ptr)) ++i;
|
|
|
|
if (i < 32) {
|
|
|
|
intr_table[i] = virt_to_phys(&intrq->ed);
|
|
|
|
nothing_placed = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (nothing_placed) {
|
2012-12-11 21:08:07 +01:00
|
|
|
usb_debug("Error: Failed to place ohci interrupt endpoint "
|
2012-06-20 14:58:21 +02:00
|
|
|
"descriptor into periodic table: no space left\n");
|
|
|
|
ohci_destroy_intr_queue(ep, intrq);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return intrq;
|
2010-08-13 11:18:58 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* remove queue from device schedule, dropping all data that came in */
|
|
|
|
static void
|
2012-06-20 14:58:21 +02:00
|
|
|
ohci_destroy_intr_queue(endpoint_t *const ep, void *const q_)
|
2010-08-13 11:18:58 +02:00
|
|
|
{
|
2012-06-20 14:58:21 +02:00
|
|
|
intr_queue_t *const intrq = (intr_queue_t *)q_;
|
|
|
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Remove interrupt queue from periodic table. */
|
|
|
|
ohci_t *const ohci = OHCI_INST(ep->dev->controller);
|
|
|
|
u32 *const intr_table = ohci->hcca->HccaInterruptTable;
|
|
|
|
for (i=0; i < 32; ++i) {
|
|
|
|
if (intr_table[i] == virt_to_phys(intrq))
|
|
|
|
intr_table[i] = virt_to_phys(ohci->periodic_ed);
|
|
|
|
}
|
|
|
|
/* Wait for frame to finish. */
|
|
|
|
mdelay(1);
|
|
|
|
|
|
|
|
/* Free unprocessed TDs. */
|
|
|
|
while ((intrq->ed.head_pointer & ~0x3) != intrq->ed.tail_pointer) {
|
|
|
|
td_t *const cur_td =
|
|
|
|
(td_t *)phys_to_virt(intrq->ed.head_pointer & ~0x3);
|
|
|
|
intrq->ed.head_pointer = cur_td->next_td;
|
|
|
|
free(INTRQ_TD_FROM_TD(cur_td));
|
|
|
|
--intrq->remaining_tds;
|
|
|
|
}
|
|
|
|
/* Free final, dummy TD. */
|
|
|
|
free(phys_to_virt(intrq->ed.head_pointer & ~0x3));
|
|
|
|
/* Free data buffer. */
|
|
|
|
free(intrq->data);
|
|
|
|
|
2012-11-22 17:21:57 +01:00
|
|
|
/* Free TDs already fetched from the done queue. */
|
2012-06-20 14:58:21 +02:00
|
|
|
ohci_process_done_queue(ohci, 1);
|
|
|
|
while (intrq->head) {
|
|
|
|
intrq_td_t *const cur_td = intrq->head;
|
|
|
|
intrq->head = intrq->head->next;
|
|
|
|
free(cur_td);
|
|
|
|
--intrq->remaining_tds;
|
|
|
|
}
|
|
|
|
|
2012-11-22 17:21:57 +01:00
|
|
|
/* Mark interrupt queue to be destroyed.
|
|
|
|
ohci_process_done_queue() will free the remaining TDs
|
|
|
|
and finish the interrupt queue off once all TDs are gone. */
|
|
|
|
intrq->destroy = 1;
|
2012-06-20 14:58:21 +02:00
|
|
|
|
|
|
|
/* Save data toggle. */
|
|
|
|
ep->toggle = intrq->ed.head_pointer & ED_TOGGLE;
|
2010-08-13 11:18:58 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* read one intr-packet from queue, if available. extend the queue for new input.
|
|
|
|
return NULL if nothing new available.
|
|
|
|
Recommended use: while (data=poll_intr_queue(q)) process(data);
|
|
|
|
*/
|
2012-06-20 14:58:21 +02:00
|
|
|
static u8 *
|
|
|
|
ohci_poll_intr_queue(void *const q_)
|
2010-08-13 11:18:58 +02:00
|
|
|
{
|
2012-06-20 14:58:21 +02:00
|
|
|
intr_queue_t *const intrq = (intr_queue_t *)q_;
|
|
|
|
|
|
|
|
u8 *data = NULL;
|
|
|
|
|
|
|
|
/* Process done queue first, then check if we have work to do. */
|
|
|
|
ohci_process_done_queue(OHCI_INST(intrq->endp->dev->controller), 0);
|
|
|
|
|
|
|
|
if (intrq->head) {
|
|
|
|
/* Save pointer to processed TD and advance. */
|
|
|
|
intrq_td_t *const cur_td = intrq->head;
|
|
|
|
intrq->head = cur_td->next;
|
|
|
|
|
|
|
|
/* Return data buffer of this TD. */
|
|
|
|
data = cur_td->data;
|
|
|
|
|
|
|
|
/* Requeue this TD (i.e. copy to dummy and requeue as dummy). */
|
|
|
|
intrq_td_t *const dummy_td =
|
|
|
|
INTRQ_TD_FROM_TD(phys_to_virt(intrq->ed.tail_pointer));
|
|
|
|
ohci_fill_intrq_td(dummy_td, intrq, cur_td->data);
|
|
|
|
/* Reset all but intrq pointer (i.e. init as dummy). */
|
|
|
|
memset(cur_td, 0, sizeof(*cur_td));
|
|
|
|
cur_td->intrq = intrq;
|
|
|
|
/* Insert into interrupt queue as dummy. */
|
|
|
|
dummy_td->td.next_td = virt_to_phys(&cur_td->td);
|
|
|
|
intrq->ed.tail_pointer = virt_to_phys(&cur_td->td);
|
|
|
|
}
|
|
|
|
|
|
|
|
return data;
|
2010-08-13 11:18:58 +02:00
|
|
|
}
|
|
|
|
|
2013-02-21 22:41:40 +01:00
|
|
|
static int
|
2012-06-20 10:08:06 +02:00
|
|
|
ohci_process_done_queue(ohci_t *const ohci, const int spew_debug)
|
|
|
|
{
|
2013-02-21 22:41:40 +01:00
|
|
|
/* returns the amount of bytes *not* transmitted for short packets */
|
|
|
|
int result = 0;
|
2012-06-20 14:58:21 +02:00
|
|
|
int i, j;
|
|
|
|
|
|
|
|
/* Temporary queue of interrupt queue TDs (to reverse order). */
|
|
|
|
intrq_td_t *temp_tdq = NULL;
|
2012-06-20 10:08:06 +02:00
|
|
|
|
|
|
|
/* Check if done head has been written. */
|
|
|
|
if (!(ohci->opreg->HcInterruptStatus & WritebackDoneHead))
|
2013-02-21 22:41:40 +01:00
|
|
|
return 0;
|
2012-06-20 10:08:06 +02:00
|
|
|
/* Fetch current done head.
|
|
|
|
Lsb is only interesting for hw interrupts. */
|
|
|
|
u32 phys_done_queue = ohci->hcca->HccaDoneHead & ~1;
|
|
|
|
/* Tell host controller, he may overwrite the done head pointer. */
|
|
|
|
ohci->opreg->HcInterruptStatus = WritebackDoneHead;
|
|
|
|
|
|
|
|
i = 0;
|
|
|
|
/* Process done queue (it's in reversed order). */
|
|
|
|
while (phys_done_queue) {
|
|
|
|
td_t *const done_td = (td_t *)phys_to_virt(phys_done_queue);
|
|
|
|
|
|
|
|
/* Advance pointer to next TD. */
|
|
|
|
phys_done_queue = done_td->next_td;
|
|
|
|
|
|
|
|
switch (done_td->config & TD_QUEUETYPE_MASK) {
|
|
|
|
case TD_QUEUETYPE_ASYNC:
|
2013-02-21 22:41:40 +01:00
|
|
|
/* Free processed async TDs and count short transfer. */
|
|
|
|
if (done_td->current_buffer_pointer)
|
|
|
|
result += (done_td->buffer_end & 0xfff) -
|
|
|
|
(done_td->current_buffer_pointer
|
|
|
|
& 0xfff) + 1;
|
2012-06-20 10:08:06 +02:00
|
|
|
free((void *)done_td);
|
|
|
|
break;
|
2012-11-22 17:21:57 +01:00
|
|
|
case TD_QUEUETYPE_INTR: {
|
|
|
|
intrq_td_t *const td = INTRQ_TD_FROM_TD(done_td);
|
|
|
|
intr_queue_t *const intrq = td->intrq;
|
|
|
|
/* Check if the corresponding interrupt
|
|
|
|
queue is still beeing processed. */
|
|
|
|
if (intrq->destroy) {
|
|
|
|
/* Free this TD, and */
|
|
|
|
free(td);
|
|
|
|
--intrq->remaining_tds;
|
|
|
|
usb_debug("Freed TD from orphaned interrupt "
|
|
|
|
"queue, %d TDs remain.\n",
|
|
|
|
intrq->remaining_tds);
|
2015-02-22 16:49:10 +01:00
|
|
|
/* the interrupt queue if it has no more TDs. */
|
|
|
|
if (!intrq->remaining_tds)
|
|
|
|
free(intrq);
|
2012-11-22 17:21:57 +01:00
|
|
|
} else {
|
|
|
|
/* Save done TD to be processed. */
|
|
|
|
td->next = temp_tdq;
|
|
|
|
temp_tdq = td;
|
|
|
|
}
|
2012-06-20 14:58:21 +02:00
|
|
|
break;
|
2012-11-22 17:21:57 +01:00
|
|
|
}
|
2012-06-20 10:08:06 +02:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
++i;
|
|
|
|
}
|
|
|
|
if (spew_debug)
|
2012-11-01 23:44:10 +01:00
|
|
|
usb_debug("Processed %d done TDs.\n", i);
|
2012-06-20 14:58:21 +02:00
|
|
|
|
|
|
|
j = 0;
|
|
|
|
/* Process interrupt queue TDs in right order. */
|
|
|
|
while (temp_tdq) {
|
|
|
|
/* Save pointer of current TD and advance. */
|
|
|
|
intrq_td_t *const cur_td = temp_tdq;
|
|
|
|
temp_tdq = temp_tdq->next;
|
|
|
|
|
|
|
|
/* The interrupt queue for the current TD. */
|
|
|
|
intr_queue_t *const intrq = cur_td->intrq;
|
|
|
|
/* Append to interrupt queue. */
|
|
|
|
if (!intrq->head) {
|
|
|
|
/* First element. */
|
|
|
|
intrq->head = intrq->tail = cur_td;
|
|
|
|
} else {
|
|
|
|
/* Insert at tail. */
|
|
|
|
intrq->tail->next = cur_td;
|
|
|
|
intrq->tail = cur_td;
|
|
|
|
}
|
|
|
|
/* It's always the last element. */
|
|
|
|
cur_td->next = NULL;
|
|
|
|
++j;
|
|
|
|
}
|
|
|
|
if (spew_debug)
|
2012-11-01 23:44:10 +01:00
|
|
|
usb_debug("processed %d done tds, %d intr tds thereof.\n", i, j);
|
2013-02-21 22:41:40 +01:00
|
|
|
|
|
|
|
return result;
|
2012-06-20 10:08:06 +02:00
|
|
|
}
|