coreboot-kgpe-d16/src/southbridge/intel/common/Kconfig

config SOUTHBRIDGE_INTEL_COMMON
	def_bool n
config SOUTHBRIDGE_INTEL_COMMON_GPIO
	def_bool n
config SOUTHBRIDGE_INTEL_COMMON_SMBUS
	def_bool n
config HAVE_INTEL_CHIPSET_LOCKDOWN
	def_bool n

config INTEL_CHIPSET_LOCKDOWN
	depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS
	#ChromeOS's payload seems to handle finalization on its on.
	bool "Lock down chipset in coreboot"
	default y
	help
	  Some registers within host bridge on particular chipsets should be
	  locked down on each normal boot path (done by either coreboot or payload)
	  and S3 resume (always done by coreboot). Select this to let coreboot
	  to do this on normal boot path.
Makefile: Fix adding intel/common Directory intel/common must be conditionally added in the list of source directories, as the parent directory southbridge/intel is unconditionally added even for boards without such device. Change-Id: I7088bc6db9f56909ffa996aa7eff76cd72e177eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3827 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> 2013-07-28 22:39:37 +02:00			`config SOUTHBRIDGE_INTEL_COMMON`
			`def_bool n`
southbridge/intel/common: Add common gpio.c Add a common southbridge gpio code to reduce existing duplicated code. By adding it to ram-stage, GPIOs can be changed any time, without the need of direct register access. The files are based on bd82x6x and lynxpoint gpio.c. Change-Id: Iaf0c2f941f2625a5547f9cba79da1b173da6f295 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12893 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> 2015-12-26 08:33:16 +01:00			`config SOUTHBRIDGE_INTEL_COMMON_GPIO`
			`def_bool n`
sb/intel/*: Use common SMBus functions All Intel southbridges implement the same SMBus functions. This patch replaces all these similar and mostly identical implementations with a common file. This also makes i2c block read available to all those southbridges. If the northbridge has to read a lot of SPD bytes sequentially, using this function can reduce the time being spent to read SPD five-fold. Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> 2017-04-12 17:01:31 +02:00			`config SOUTHBRIDGE_INTEL_COMMON_SMBUS`
			`def_bool n`
sb/intel/: add option to lockdown chipset on normal boot path On platforms with a PCH, some registers within host bridge should be locked down on each normal boot path (done by either coreboot or payload) and S3 resume (always done by coreboot). A function to perform such locking is implemented in src/northbridge/ intel//finalize.c, and is designed as the handler of an #SMI triggered with outb(APM_CNT_FINALIZE, APM_CNT), but currently this #SMI is only triggered during s3 resume, and not on normal boot path. This problem has beed discussed in https://mail.coreboot.org/pipermail/coreboot/2017-August/084924.html . This time, an option "INTEL_CHIPSET_LOCKDOWN" within src/southbridge/ intel/common/Kconfig is added to control the actual locking, which depends on several compatibility flags, including "HAVE_INTEL_CHIPSET_LOCKDOWN". In this commit, "ibexpeak", "bd82x6x", "fsp_bd82x6x", and "lynxpoint" have the flag "HAVE_INTEL_CHIPSET_LOCKDOWN" selected. The change is only well tested on Sandy Bridge, my Lenovo x230. Change-Id: I43d4142291c8737b29738c41e8c484328b297b55 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> 2017-08-22 10:26:22 +02:00			`config HAVE_INTEL_CHIPSET_LOCKDOWN`
			`def_bool n`

			`config INTEL_CHIPSET_LOCKDOWN`
			`depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS`
			`#ChromeOS's payload seems to handle finalization on its on.`
			`bool "Lock down chipset in coreboot"`
			`default y`
			`help`
			`Some registers within host bridge on particular chipsets should be`
			`locked down on each normal boot path (done by either coreboot or payload)`
			`and S3 resume (always done by coreboot). Select this to let coreboot`
			`to do this on normal boot path.`