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Documentation: Add mainboard section to index Change-Id: Ib00bd6cdd13f164ca7eb07c9092e8d8fe17d23b1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/26266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-17 13:06:49 +02:00
# Mainboard-specific documentation
This section contains documentation about coreboot on specific mainboards.
mb/51nb: Add support for the 51nb X210 The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes: * EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different All hardware appears to work as expected, although the SD reader is untested. Signed-off-by: Matthew Garrett <mjg59@google.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-24 23:06:39 +02:00
## 51NB
- [X210](51nb/x210.md)
Documentation/mb: Link AMD mainboards directly in the big list Fixes an issue with amd/index.md not being part of a toctree Change-Id: Id419695d24a49951afb844c81cc0951d6920e0d2 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-05 21:06:35 +02:00
## AMD
- [padmelon](amd/padmelon/padmelon.md)
Documentation/mainboard: Fix index Remove duplicate headings, move vendor sections that were placed amidst other vendor hierarchies, and while we are at it, sort it alphabetically. Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18 23:58:26 +02:00
## ASRock
- [H81M-HDS](asrock/h81m-hds.md)
- [H110M-DVS](asrock/h110m-dvs.md)
mainboard: Add ASUS P8H61-M LX Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This code is based on the output of autoport. The file `data.vbt` matches the VBT in the latest version of the vendor firmware (version 4601). This board works well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. To summarise: the only known issues are that S3 suspend/resume doesn't work, and that there is no automatic fan control via the super I/O. Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/27798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-02 09:41:08 +02:00
## ASUS
Documentation: Add Asus F2A85-M Change-Id: I4d195f4833ba71fdc559815cafb0f5d0d254e897 Signed-off-by: Balazs Vinarz <vinibali1@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-13 19:00:18 +01:00
- [F2A85-M](asus/f2a85-m.md)
Documentation: link asus p5q on mainboard page Change-Id: Ia3f58cc15897bff87dd699ab1fb1c42545119f0b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-22 18:46:37 +01:00
- [P5Q](asus/p5q.md)
mainboard: Add ASUS P8H61-M LX Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This code is based on the output of autoport. The file `data.vbt` matches the VBT in the latest version of the vendor firmware (version 4601). This board works well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. To summarise: the only known issues are that S3 suspend/resume doesn't work, and that there is no automatic fan control via the super I/O. Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/27798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-02 09:41:08 +02:00
- [P8H61-M LX](asus/p8h61-m_lx.md)
mb/asus/p8h61-m_pro: Add small fixes * Add VBT * Configure OnBoard NIC * Add documentation Change-Id: Iad739b4e1dacb41f5f63247150951df7013bbf0c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-20 10:05:18 +02:00
- [P8H61-M Pro](asus/p8h61-m_pro.md)
mainboard: Add support for ASUS P8Z77-M PRO desktop mainboard Add support for ASUS P8Z77-M PRO desktop mainboard Working: - Tianocore and SeaBIOS boot - PS/2 keyboard and mouse - Audio - S3 Suspend, shutdown and reboot - USB2 / USB3 - Gigabit Ethernet - SATA3, SATA2 and eSATA - NVME - CPU Temp sensors - TPM - Native raminit and also MRC - PCIe GPU in all PCIe slots (16x/8x/4x) (linux) - Integrated graphics with both libgfxinit and Intel Video OpROM (all connectors VGA/DVI-D/HDMI) Signed-off-by: Vlado Cibic <vladocb@protonmail.com> Change-Id: I47d24ac8b236f929c3160f9a769b971d83710f9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/33328 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09 08:53:50 +02:00
- [P8Z77-M Pro](asus/p8z77-m_pro.md)
mainboard: Add ASUS P8H61-M LX Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This code is based on the output of autoport. The file `data.vbt` matches the VBT in the latest version of the vendor firmware (version 4601). This board works well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. To summarise: the only known issues are that S3 suspend/resume doesn't work, and that there is no automatic fan control via the super I/O. Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/27798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-02 09:41:08 +02:00
Documentation: Add cavium SoC and mainboard * Add documentation for CN81XX SoC * Add documentation for CN81XX EVB SFF mainboard * Add documentation for BDK * Add documentation for BOOTROM and BOOTBLOCK behaviour * Alphabetically sort vendors Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-18 13:23:27 +02:00
## Cavium
Documentation: Add mainboard section to index Change-Id: Ib00bd6cdd13f164ca7eb07c9092e8d8fe17d23b1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/26266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-17 13:06:49 +02:00
Documentation: Add cavium SoC and mainboard * Add documentation for CN81XX SoC * Add documentation for CN81XX EVB SFF mainboard * Add documentation for BDK * Add documentation for BOOTROM and BOOTBLOCK behaviour * Alphabetically sort vendors Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-18 13:23:27 +02:00
- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
Documentation: Add HP Compaq 8200 and NPCD378 Change-Id: I56db0cc11cfa5a1a537091553393542312d4f212 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26543 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25 11:04:45 +02:00
Documentation/mainboard: Add emulation/spike-riscv.md Move the usage instructions from their ad-hoc place in Kconfig.name to the Documentation directory, and expand them a bit. Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-10-28 02:48:25 +02:00
## Emulation
The boards in this section are not real mainboards, but emulators.
- [Spike RISC-V emulator](emulation/spike-riscv.md)
mb/qemu-riscv: update to match current qemu version Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/30554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-31 14:13:47 +01:00
- [Qemu RISC-V emulator](emulation/qemu-riscv.md)
mainboard/emulation/qemu-aarch64: Add new board for ARMv8 This CL adds a new board, QEMU/AArch64, for ARMv8. The machine supported is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu via a flag. To execute: $ qemu-system-aarch64 -M virt,secure=on,virtualization=on \ -cpu cortex-a53 -bios build/coreboot.rom -m 8192M -nographic Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-11 09:01:31 +02:00
- [Qemu AArch64 emulator](emulation/qemu-aarch64.md)
Documentation/mainboard: Add emulation/spike-riscv.md Move the usage instructions from their ad-hoc place in Kconfig.name to the Documentation directory, and expand them a bit. Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-10-28 02:48:25 +02:00
mainboard/facebook/fbg1701: Do initial mainboard commit Initial support for Facebook FBG-1701 system. coreboot implementation based on Intel Strago mainboard. Configure 'Onboard memory manufacturer' which must match HW. BUG=N/A TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701 Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-04 13:53:05 +02:00
## Facebook
- [FBG-1701](facebook/fbg1701.md)
mb/facebook/monolith: Add Facebook Monolith The board is booting Linux and has been briefly tested. SeaBIOS, TianoCore payload and Linux as payload all seem to work fine. BUG=N/A TEST=tested on Facebook Monolith Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-05 13:45:41 +01:00
- [Monolith](facebook/monolith.md)
mainboard/facebook/fbg1701: Do initial mainboard commit Initial support for Facebook FBG-1701 system. coreboot implementation based on Intel Strago mainboard. Configure 'Onboard memory manufacturer' which must match HW. BUG=N/A TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701 Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-04 13:53:05 +02:00
mb/foxconn/d41s: Add mainboard This supports the Foxconn d41s, d42s, d51s, d52s. The following is tested (SeaBIOS 1.12 + Linux 4.9) and works: - COM1 - S3 resume (with SeaBIOS needs sercon disabled) - Native graphic init on VGA output - SATA - USB - Ethernet - PS2 keyboard The base for this mainboard port was the Intel D510MO port. Change-Id: Ie4ec9cbf70adcdddbc2e5d805e4806825c320072 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28227 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-19 23:52:45 +02:00
## Foxconn
- [D41S](foxconn/d41s.md)
Documentation: Add Gigabyte to list of mainboards Gigabyte was not in the list of vendors in the mainboard-specific documentation. This made a newly added mainboard page difficult to locate. This commit adds Gigabyte and links said mainboard in the mainboard-specific documentation main page. Change-Id: I8839e1c1176fbdc3dd9da616f68c58e8e1cf1b16 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-13 01:09:41 +02:00
## Gigabyte
- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)
Documentation/../../dragonegg: Add dragonegg coreboot development documentation Change-Id: Ia15e317557a0893d9f80cc9e87c6b90c85b93dcf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-26 07:13:16 +01:00
## Google
- [Dragonegg](google/dragonegg.md)
Documentation: Add HP Compaq 8200 and NPCD378 Change-Id: I56db0cc11cfa5a1a537091553393542312d4f212 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26543 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25 11:04:45 +02:00
## HP
- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
mb/hp: Add Z220 SFF workstation * Add initial board commit based on HP8200 SFF. * Add documentation. * Serial and PCIe slot are working. Tested on HP Z220. Change-Id: I75987a7ea9a008a64281f0d5ab27e5148d36a4ec Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33207 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 15:56:44 +02:00
- [Z220 Workstation SFF](hp/z220_sff.md)
Documentation: Add cavium SoC and mainboard * Add documentation for CN81XX SoC * Add documentation for CN81XX EVB SFF mainboard * Add documentation for BDK * Add documentation for BOOTROM and BOOTBLOCK behaviour * Alphabetically sort vendors Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-18 13:23:27 +02:00
Documentation: Add HP EliteBook 8760w Also add the HP EliteBook document from wiki. Change-Id: I189db9c279705af53d82af66d0c2e8afb6f84d73 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30950 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 11:31:08 +01:00
### EliteBook series
- [EliteBook common](hp/elitebook_series.md)
- [EliteBook 8760w](hp/8760w.md)
Documentation/mainboard: Fix index Remove duplicate headings, move vendor sections that were placed amidst other vendor hierarchies, and while we are at it, sort it alphabetically. Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18 23:58:26 +02:00
## Intel
- [DG43GT](intel/dg43gt.md)
- [IceLake RVP](intel/icelake_rvp.md)
- [KBLRVP11](intel/kblrvp11.md)
Documentation: Add basic flashing tutorial for Lenovo * Add basic flashing tutorial ** Describe internal and external flashing ** Describe flash supply diode protection ** Gives general advices on flashing ** Describe how to use flashrom --ifd * Describe basic flashing on Lenovo T4xx devices ** Describe how to disassemble and access the flash IC on T4xx ** Describe flash layout on Sandy Bridge and Ivy Bridge series. Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-04 10:04:45 +02:00
## Lenovo
Documentation: Make lenovo codenames human readable Use rst parser to convert the csv to markdown tables. Change-Id: I7fd61bd7a4e8818901520311332ae4027e7a7d02 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-09 12:20:08 +02:00
- [Mainboard codenames](lenovo/codenames.md)
mb/lenovo/x220: Add x1 as a variant ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a clone of X220, with additional USB3 controller on pci-e (as i7 variant of x220), and a powered ESATA port wired to ata4 (Linux' annotation). Documentation added. Tested: - CPU i5-2520M - Slotted DIMM 8GiB - Camera - Mini pci-e on wlan slot - Msata on wwan slot - On board SDHCI connected to pci-e - USB3 controller connected to pci-e - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from SeaBIOS, or Linux payload (Heads) Not tested: - Fingerprint reader on USB2 - Onboard USB2 interfaces (wlan slot, wwan slot) Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/29434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-02 12:24:42 +01:00
- [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant board - This port should be Reclaim Your Freedom compliant (not certified yet). - Untested on boards with external Radeon graphics adapter. - Some columns on the left-most side of display are completely black on 1400x1050 IPS display[1]. Display works fine on Linux. I don't know why it appears like that. So far it has been observed only with native graphics initialization. - Only GRUB2 and SeaBIOS payloads tested for now. - 2504 docking station USB doesn't work under Linux. Can detect pendrive in GRUB2 payload. - Sometimes it takes 20s of "pretending it's powered off" to run coreboot code. Issue is payload agnostic. Probably caused by missing one capacitor on my unit. [1] https://imgur.com/a/0wpMGsm Change-Id: Ibd9208a5eafd228f8eedbc8fb4f4eb9ed1932a14 Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-07 20:28:51 +02:00
- [R60](lenovo/r60.md)
Documentation: Add basic flashing tutorial for Lenovo * Add basic flashing tutorial ** Describe internal and external flashing ** Describe flash supply diode protection ** Gives general advices on flashing ** Describe how to use flashrom --ifd * Describe basic flashing on Lenovo T4xx devices ** Describe how to disassemble and access the flash IC on T4xx ** Describe flash layout on Sandy Bridge and Ivy Bridge series. Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-04 10:04:45 +02:00
- [T4xx common](lenovo/t4xx_series.md)
mb/lenovo/x220: Add x1 as a variant ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a clone of X220, with additional USB3 controller on pci-e (as i7 variant of x220), and a powered ESATA port wired to ata4 (Linux' annotation). Documentation added. Tested: - CPU i5-2520M - Slotted DIMM 8GiB - Camera - Mini pci-e on wlan slot - Msata on wwan slot - On board SDHCI connected to pci-e - USB3 controller connected to pci-e - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from SeaBIOS, or Linux payload (Heads) Not tested: - Fingerprint reader on USB2 - Onboard USB2 interfaces (wlan slot, wwan slot) Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/29434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-02 12:24:42 +01:00
- [X2xx common](lenovo/x2xx_series.md)
Documentation: Add basic flashing tutorial for Lenovo * Add basic flashing tutorial ** Describe internal and external flashing ** Describe flash supply diode protection ** Gives general advices on flashing ** Describe how to use flashrom --ifd * Describe basic flashing on Lenovo T4xx devices ** Describe how to disassemble and access the flash IC on T4xx ** Describe flash layout on Sandy Bridge and Ivy Bridge series. Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-04 10:04:45 +02:00
mb/libretrend/lt1000: Add Libretrend LT1000 mainboard Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2018-12-21 12:23:27 +01:00
## Libretrend
- [LT1000](libretrend/lt1000.md)
treewide: Replace uses of "Nehalem" The code in coreboot is actually for the Arrandale processors, which are a MCM (Multi-Chip Module) with two different dies: - Hillel: 32nm Westmere dual-core CPU - Ironlake: 45nm northbridge with integrated graphics This has nothing to do with the older, single-die Nehalem processors. Therefore, replace the references to Nehalem with the correct names. Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17 14:04:28 +01:00
### Arrandale series
mainboard/lenovo/t410: Add new port The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.12.1 * Booting from EHCI * Running GNU/Linux 5.0.0 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Wifi * Sound * USB * Ethernet * S3 resume * VBOOT Testing in progress. Untested: * VGA * Displayport * Docking station Bugs: * AC adapter can't be read from ACPI * TPM not working with VBOOT and C_ENV BB Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/11791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2015-07-04 23:37:06 +02:00
- [T410](lenovo/t410.md)
mb/lenovo/x200: Add ThinkPad X301 as a variant It is similar to X200s, with U-series CPU, slightly different gpio setup, no docking support, and no superio chip. Tested: - CPU Core 2 Duo U9400 - Slotted DIMM 4GiB*2 from samsung - Camera - pci-e slots - sata and usb2 - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Linux payload (Heads) and Seabios. TODO: repurpose and/or rename flag H8_DOCK_EARLY_INIT (introduced in CB:4294 ) for h8-using devices without a dock. Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-16 17:22:10 +02:00
### GM45 series
Documentation: Add Montevina ThinkPads common page - Add a common page about Montevina ThinkPads. - Describe how to disable ME and remove its firmware on these models. - Describe vendor flash layouts. Thanks to swiftgeek for his help when writing this, especially the last paragraph and flash layouts. Change-Id: I85917821efe63fff4b933b6226e99c17b63eb1b9 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-16 00:35:03 +01:00
- [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md)
mb/lenovo/x200: Add ThinkPad X301 as a variant It is similar to X200s, with U-series CPU, slightly different gpio setup, no docking support, and no superio chip. Tested: - CPU Core 2 Duo U9400 - Slotted DIMM 4GiB*2 from samsung - Camera - pci-e slots - sata and usb2 - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Linux payload (Heads) and Seabios. TODO: repurpose and/or rename flag H8_DOCK_EARLY_INIT (introduced in CB:4294 ) for h8-using devices without a dock. Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-16 17:22:10 +02:00
- [X301](lenovo/x301.md)
Documentation: Add basic flashing tutorial for Lenovo * Add basic flashing tutorial ** Describe internal and external flashing ** Describe flash supply diode protection ** Gives general advices on flashing ** Describe how to use flashrom --ifd * Describe basic flashing on Lenovo T4xx devices ** Describe how to disassemble and access the flash IC on T4xx ** Describe flash layout on Sandy Bridge and Ivy Bridge series. Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-04 10:04:45 +02:00
### Sandy Bridge series
- [T420](lenovo/t420.md)
Documentation: Remove confusing xyz0 naming convention for Lenovo devices Replace xx30 with Ivy_Bridge and xx20 with Sandy_Bridge. Also add a note that the Ivy_Bridge tutorial doesn't covert T430s and T431s. Change-Id: I0b65bca83195ec22cc139130e7cb6183c0972484 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-16 11:28:11 +01:00
- [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md)
Documentation: mb/lenovo: Make X1 uppercase x1 -> X1. Change-Id: Iab28e979102a6f98c41706ac0f483770466385dc Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-16 20:19:57 +01:00
- [X1](lenovo/x1.md)
Documentation: Add basic flashing tutorial for Lenovo * Add basic flashing tutorial ** Describe internal and external flashing ** Describe flash supply diode protection ** Gives general advices on flashing ** Describe how to use flashrom --ifd * Describe basic flashing on Lenovo T4xx devices ** Describe how to disassemble and access the flash IC on T4xx ** Describe flash layout on Sandy Bridge and Ivy Bridge series. Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-04 10:04:45 +02:00
### Ivy Bridge series
- [T430](lenovo/t430.md)
Documentation: Add W530 / T530 Change-Id: Ib253308737f8c7a497c6ca13eab88220b1ac27ad Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-18 15:48:43 +01:00
- [T530](lenovo/w530.md)
- [W530](lenovo/w530.md)
Documentation: Remove confusing xyz0 naming convention for Lenovo devices Replace xx30 with Ivy_Bridge and xx20 with Sandy_Bridge. Also add a note that the Ivy_Bridge tutorial doesn't covert T430s and T431s. Change-Id: I0b65bca83195ec22cc139130e7cb6183c0972484 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-16 11:28:11 +01:00
- [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md)
mainboard/lenovo/t430s: Add ThinkPad T431s as a variant The code is based on autoport and that for T430s Tested: - CPU i5-3337U - Slotted DIMM 2GiB - Soldered RAM 4GiB from samsung (There may be more models here) - Camera - pci-e and usb2 on M.2 slot with A key for wlan - sata and usb2 (no superspeed components) on M.2 slot with B key for wwan - On board SDHCI connected to pci-e - USB3 ports - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - TPM1 on LPC - EHCI debug on SSP2 (USB3 port on the left) - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from Linux payload (Heads), Seabios may also work. Not tested: - Fingerprint reader on USB2 (not present on mine) - Keyboard backlight (not present on mine) - "sticky_fn" flag in nvram Not implemented yet: - Fn locking in nvram (may not be identical to "sticky_fn") - C-based native graphic init (since T431s has eDP instead of LVDS) - Detecting the model of Soldered RAM at runtime, and loading the corresponding SPD datum (3 observed) from CBFS (the mechanism may be similar to that on x1_carbon_gen1 and s230u, but I do not know how to find gpio ports for that, and SPD data stored in vendor firmware.) Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/30021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-29 13:37:35 +01:00
- [T431s](lenovo/t431s.md)
Documentation: xx30 ThinkPads internal flashing Add detailed instructions on how to unlock protected SPI ranges and flash coreboot internally on Lenovo ThinkPad Ivy Bridge series by exploiting stock BIOS security issues. Change-Id: I8d8551910c31fd2e6ff728e17dafaea45970166b Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-08 03:20:20 +01:00
- [Internal flashing](lenovo/ivb_internal_flashing.md)
Documentation: Add basic flashing tutorial for Lenovo * Add basic flashing tutorial ** Describe internal and external flashing ** Describe flash supply diode protection ** Gives general advices on flashing ** Describe how to use flashrom --ifd * Describe basic flashing on Lenovo T4xx devices ** Describe how to disassemble and access the flash IC on T4xx ** Describe flash layout on Sandy Bridge and Ivy Bridge series. Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-04 10:04:45 +02:00
mainboard: Add Lenovo ThinkPad T440p The code is based on autoport. This port is tested on a T440p without a dGPU and can boot Arch Linux from SATA disk with SeaBIOS payload. The tested components and issues are in the documentation. Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34359 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-30 15:16:50 +02:00
### Haswell series
- [T440p](lenovo/t440p.md)
Documentation: Add MSI MS-7707 Change-Id: Iba38bda9becba9fcffb51afc4756023659f092ef Signed-off-by: Max Blau <tripleshiftone@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-07 00:18:42 +02:00
## MSI
- [MS-7707](msi/ms7707/ms7707.md)
Documentation/mainboard: Fix index Remove duplicate headings, move vendor sections that were placed amidst other vendor hierarchies, and while we are at it, sort it alphabetically. Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18 23:58:26 +02:00
## Open Cellular
- [Elgon](opencellular/elgon.md)
- [Rotundu](opencellular/rotundu.md)
Documentation: Add PC Engines apu2 Describe how to run coreboot on the PC Engines apu2 mainboard. Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-31 14:07:05 +02:00
## PC Engines
Documentation/mainboard: Fix index Remove duplicate headings, move vendor sections that were placed amidst other vendor hierarchies, and while we are at it, sort it alphabetically. Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18 23:58:26 +02:00
- [APU1](pcengines/apu1.md)
Documentation: Add PC Engines apu2 Describe how to run coreboot on the PC Engines apu2 mainboard. Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-31 14:07:05 +02:00
- [APU2](pcengines/apu2.md)
Documentation/mainboard: Fix index Remove duplicate headings, move vendor sections that were placed amidst other vendor hierarchies, and while we are at it, sort it alphabetically. Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18 23:58:26 +02:00
## Portwell
mb/roda/rk9: Document flash header Change-Id: I5bd131635340ffa0c6b8979fc8e263fc5f09fdc5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-21 23:17:06 +01:00
Documentation/mainboard: Fix index Remove duplicate headings, move vendor sections that were placed amidst other vendor hierarchies, and while we are at it, sort it alphabetically. Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18 23:58:26 +02:00
- [PQ7-M107](portwell/pq7-m107.md)
mb/roda/rk9: Document flash header Change-Id: I5bd131635340ffa0c6b8979fc8e263fc5f09fdc5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-21 23:17:06 +01:00
mb/protectli/vault: Add FW2B and FW4B Braswell based boards support Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I553fd3a89299314a855f055014ca7645100e12e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-03-27 11:35:48 +01:00
## Protectli
- [FW2B / FW4B](protectli/fw2b_fw4b.md)
mb/protectli/vault_kbl: Add FW6 support Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-06-27 12:19:18 +02:00
- [FW6A / FW6B / FW6C](protectli/fw6.md)
mb/protectli/vault: Add FW2B and FW4B Braswell based boards support Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I553fd3a89299314a855f055014ca7645100e12e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-03-27 11:35:48 +01:00
Documentation/mainboard: Fix index Remove duplicate headings, move vendor sections that were placed amidst other vendor hierarchies, and while we are at it, sort it alphabetically. Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18 23:58:26 +02:00
## Roda
Documentation: Add PC Engines apu1 Describe how to run coreboot on the PC Engines apu1 mainboard. Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-21 12:14:36 +02:00
Documentation/mainboard: Fix index Remove duplicate headings, move vendor sections that were placed amidst other vendor hierarchies, and while we are at it, sort it alphabetically. Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18 23:58:26 +02:00
- [RK9 Flash Header](roda/rk9/flash_header.md)
Documentation: Add PC Engines apu1 Describe how to run coreboot on the PC Engines apu1 mainboard. Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-21 12:14:36 +02:00
Documentation: Add cavium SoC and mainboard * Add documentation for CN81XX SoC * Add documentation for CN81XX EVB SFF mainboard * Add documentation for BDK * Add documentation for BOOTROM and BOOTBLOCK behaviour * Alphabetically sort vendors Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-18 13:23:27 +02:00
## SiFive
- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
mainboard: Add Supermicro X10SLM+-F This board runs well with coreboot. The documentation part of this commit lists what works and what doesn't. Tested with GRUB 2.02 as a payload, loading SeaBIOS 1.12.0 which then boots FreeBSD 11.2. It has also been tested with GRUB directly booting Debian GNU/Linux 9.6 (kernel 4.9). Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-21 12:04:18 +01:00
## Supermicro
- [X10SLM+-F](supermicro/x10slm-f.md)
mb/supermicro/x11-lga1151-series: rework documentation This splits the x11-lga1151-series' documentation into a generic and a board specific section as a preparation for CB:35427. Additionally this adds some more information on the x11ssh board. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I40ddd0b5cce0b1a3306eae22fc0a0bc6b2a6263c Reviewed-on: https://review.coreboot.org/c/coreboot/+/35547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-23 21:54:58 +02:00
- [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
util/supermicro: Add and use new tool smcbiosinfo The BMC and tools interacting with it depend on metadata placed inside the ROM in order the flash the BIOS. Add a new tool smcbiosinfo, integrate it into the build system, and generate a 128byte metadata file called smcbiosinfo.bin on build. You need to provide the BoardID for every SMC mainboard through a new Kconfig symbol: SUPERMICRO_BOARDID Some fields are unknown, but it's sufficient to flash it using SMC vendor tools. Tested on Supermicro X11SSH: * Flashing using the WebUI works * Flashing using SMCIPMITool works No further validation is done on the firmware. Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-20 12:53:09 +02:00
- [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md)
mb/up/squared: Add mainboard Works: - bootblock, romstage, ramstage - Serial console UART0, UART1 - SPI flash console - iGPU init with libgfxinit - LAN1, LAN2 - USB2, USB3 - HDMI, DisplayPort - eMMC - flashing with flashrom externally WIP: - Documentation - VGA For some reason Seabios can not find the CBFS region and therefore it can't load seavgabios, but generally it is working as soon as Linux is booted. - ACPI Works not: - Devices needs proper configuration - Seabios can't find CBFS region Untested: - GPIO pin header - 60 pin EXHAT - Camera interface - MIPI-CSI2 2-lane (2MP) - MIPI-CSI2 4-lane (8MP) - SATA3 - USB3 OTG - embedded DisplayPort - M.2 slot - mini PCIe - flashing with flashrom internally using Linux Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-12 22:22:42 +01:00
## UP
- [Squared](up/squared/index.md)