mainboard/emulation/qemu-aarch64: Add new board for ARMv8
This CL adds a new board, QEMU/AArch64, for ARMv8. The machine supported is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu via a flag. To execute: $ qemu-system-aarch64 -M virt,secure=on,virtualization=on \ -cpu cortex-a53 -bios build/coreboot.rom -m 8192M -nographic Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Asami Doi
Julius Werner
parent
9c55ee34ac
commit
f795242f26
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@ -0,0 +1,47 @@
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# QEMU AArch64 emulator
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This page discribes how to build and run coreboot for QEMU/AArch64.
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You can use LinuxBoot via `make menuconfig` or an arbitrary FIT image
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as a payload for QEMU/AArch64.
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## Running coreboot in QEMU
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```bash
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qemu-system-aarch64 -bios ./build/coreboot.rom \
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-M virt,secure=on,virtualization=on -cpu cortex-a53 \
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-nographic -m 8912M
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```
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- The default CPU in QEMU for AArch64 is a cortex-a15 which is 32-bit
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ARM CPU. You need to specify 64-bit ARM CPU via `-cpu cortex-a53`.
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- The default privilege level in QEMU for AArch64 is EL1 that we can't
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have the right to access EL3/EL2 registers. You need to enable EL3/EL2
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via `-machine secure=on,virtualization=on`.
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- You need to specify the size of memory more than 544 MiB because 512
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MiB is reserved for the kernel.
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## Building coreboot with an arbitrary FIT payload
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There are 3 steps to make coreboot.rom for QEMU/AArch64. If you select
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LinuxBoot, step 2 and 3 have done by LinuxBoot.
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1. Get a DTB (Device Tree Blob)
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2. Build a FIT image with a DTB
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3. Add a FIT image to coreboot.rom
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### 1. Get a DTB
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You can get the DTB from QEMU with the following command.
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```
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$ qemu-system-aarch64 \
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-M virt,dumpdtb=virt.dtb,secure=on,virtualization=on \
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-cpu cortex-a53 -nographic -m 2048M
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```
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### 2. Build a FIT image with a DTB
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You need to write an image source file that has an `.its` extension to
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configure kernels, ramdisks, and DTBs.
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See [Flattened uImage Tree documentation](../../lib/payloads/fit.md) for more details.
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### 3. Add a FIT image to coreboot.rom
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You can use cbfstool to add the payload you created in step 2 to
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the coreboot.rom.
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```
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$ ./build/cbfstool ./build/coreboot.rom add -f <path-to-a-payload>/uImage \
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-n fallback/payload -t fit -c lzma
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```
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@ -24,6 +24,7 @@ The boards in this section are not real mainboards, but emulators.
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- [Spike RISC-V emulator](emulation/spike-riscv.md)
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- [Qemu RISC-V emulator](emulation/qemu-riscv.md)
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- [Qemu AArch64 emulator](emulation/qemu-aarch64.md)
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## Intel
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2019 Asami Doi <d0iasm.pub@gmail.com>.
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Emulation for QEMU 2.8 ARM Virtual Machine (alias of virt-2.8)
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# https://wiki.qemu.org/Documentation/Platforms/ARM
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if BOARD_EMULATION_QEMU_AARCH64
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_ARMV8_64
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select ARCH_VERSTAGE_ARMV8_64
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select ARCH_ROMSTAGE_ARMV8_64
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select ARCH_RAMSTAGE_ARMV8_64
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select ARM64_USE_ARCH_TIMER
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select BOARD_ROMSIZE_KB_4096
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select BOOTBLOCK_CONSOLE
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select BOOTBLOCK_CUSTOM
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select BOOT_DEVICE_NOT_SPI_FLASH
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select CONSOLE_SERIAL
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select DRIVERS_UART_PL011
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select HAVE_LINEAR_FRAMEBUFFER
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select MAINBOARD_FORCE_NATIVE_VGA_INIT
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MISSING_BOARD_RESET
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config MAINBOARD_DIR
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string
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default emulation/qemu-aarch64
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config MAINBOARD_PART_NUMBER
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string
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default "QEMU AArch64"
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config MAX_CPUS
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int
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default 2
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config MAINBOARD_VENDOR
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string
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default "QEMU"
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config DRAM_SIZE_MB
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int
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default 1024
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endif # BOARD_EMULATION_QEMU_AARCH64
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@ -0,0 +1,5 @@
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config BOARD_EMULATION_QEMU_AARCH64
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bool "QEMU AArch64 (virt)"
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help
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To execute, do:
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qemu-system-aarch64 -bios ./build/coreboot.rom -M virt,secure=on,virtualization=on -cpu cortex-a53 -nographic -m 8192M
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2019 Asami Doi <d0iasm.pub@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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romstage-y += cbmem.c
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ramstage-y += cbmem.c
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bootblock-y += media.c
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romstage-y += media.c
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ramstage-y += media.c
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bootblock-y += mmio.c
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romstage-y += mmio.c
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ramstage-y += mmio.c
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bootblock-y += memlayout.ld
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romstage-y += memlayout.ld
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ramstage-y += memlayout.ld
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bootblock-y += bootblock_custom.S
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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@ -0,0 +1,3 @@
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Board name: QEMU AArch64 (virt)
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Category: emulation
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Board URL: http://wiki.qemu.org/Main_Page
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@ -0,0 +1,36 @@
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/*
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* Early initialization code for aarch64 (a.k.a. armv8)
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*
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* Copyright 2019 Asami Doi <d0iasm.pub@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <arch/asm.h>
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ENTRY(_start)
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/* Setup CPU. */
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bl arm64_init_cpu
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/* Get code positions. */
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ldr x1, =_flash
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ldr x0, =_bootblock
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/* Calculate bootblock size. */
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ldr x2, =_ebootblock
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sub x2, x2, x0
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/* Call memcpy in arch/arm64/memcpy.S */
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bl memcpy
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dmb sy
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/* Calculate relocation offset between bootblock in flash and in DRAM. */
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ldr x0, =_flash
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ldr x1, =_bootblock
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sub x1, x1, x0
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/* Jump to main() in DRAM. */
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adr x0, main
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add x0, x0, x1
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blr x0
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ENDPROC(_start)
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Asami Doi <d0iasm.pub@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <cbmem.h>
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#include <ramdetect.h>
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#include <symbols.h>
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void *cbmem_top(void)
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{
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return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
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}
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2019 Asami Doi <d0iasm.pub@gmail.com>.
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This file exists only to avoid a compile error. It needs a devicetree.cb that is not empty.
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chip drivers/generic/generic # I2C0 controller
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device i2c 6 on end # Fake component for testing
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end
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@ -0,0 +1,34 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Asami Doi <d0iasm.pub@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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/*
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* Memory map for QEMU virt machine since
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* a578cdfbdd8f9beff5ced52b7826ddb1669abbbf (June 2019):
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*
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* 0..128MiB (0x0000_0000..0x0080_0000) is the space for a flash device.
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* 128MiB..256MiB (0x0080_0000..0x0100_0000) is used for miscellaneous device I/O.
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* 256MiB..1GiB (0x0100_0000..0x4000_0000) is reserved for possible future PCI support.
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* 1GiB.. (0x4000_0000) is RAM and the size depends on initial RAM and device memory settings
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*
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* 0x0000_0000..0x0080_0000: Flash memory
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* 0x0900_0000..0x0900_1000: UART (PL011)
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* 0x0901_0000..0x0901_1000: RTC (PL031)
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* 0x0903_0000..0x0903_1000: GPIO (PL061)
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* 0x0904_0000..0x0904_1000: Secure UART (PL011)
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* 0x0905_0000..0x0907_0000: SMMU (smmu-v3)
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* 0x0a00_0000..0x0a00_0200: MMIO (virtio)
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* 0x0c00_0000..0x0e00_0000: Platform bus
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* 0x4000_0000..: RAM
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*/
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#define VIRT_UART_BASE 0x09000000
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#define VIRT_RTC_BASE 0x09010000
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#define VIRT_GPIO_BASE 0x09030000
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#define VIRT_SECURE_UART_BASE 0x09040000
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#define VIRT_SMMU_BASE 0x09050000
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#define VIRT_MMIO_BASE 0x0a000000
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#define VIRT_PLATFORM_BUS_BASE 0x0c000000
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Asami Doi <d0iasm.pub@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <cbmem.h>
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#include <ramdetect.h>
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#include <symbols.h>
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#include <device/device.h>
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static void mainboard_enable(struct device *dev)
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{
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int ram_size_mb = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB);
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ram_resource(dev, 0, (uintptr_t)_dram / KiB, ram_size_mb * KiB);
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}
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struct chip_operations mainboard_ops = {
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.name = "qemu_aarch64",
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.enable_dev = mainboard_enable,
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};
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Asami Doi <d0iasm.pub@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <boot_device.h>
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/* Maps directly to NOR flash up to ROM size. */
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static const struct mem_region_device boot_dev =
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MEM_REGION_DEV_RO_INIT((void *)0x0, CONFIG_ROM_SIZE);
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const struct region_device *boot_device_ro(void)
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{
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return &boot_dev.rdev;
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}
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@ -0,0 +1,33 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Asami Doi <d0iasm.pub@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <memlayout.h>
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#include <arch/header.ld>
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/*
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* Memory map for QEMU virt machine since
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* a578cdfbdd8f9beff5ced52b7826ddb1669abbbf (June 2019):
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*
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* 0..128MiB (0x0000_0000..0x0080_0000) is the space for a flash device.
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* 128MiB..256MiB (0x0080_0000..0x0100_0000) is used for miscellaneous device I/O.
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* 256MiB..1GiB (0x0100_0000..0x4000_0000) is reserved for possible future PCI support.
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* 1GiB.. (0x4000_0000) is RAM and the size depends on initial RAM and device memory settings.
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*/
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SECTIONS
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{
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REGION(flash, 0x00000000, CONFIG_ROM_SIZE, 8)
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DRAM_START(0x40000000)
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BOOTBLOCK(0x60010000, 64K)
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STACK(0x60020000, 64K)
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ROMSTAGE(0x60030000, 128K)
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RAMSTAGE(0x60070000, 16M)
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TTB(0x61100000, 16K)
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POSTRAM_CBFS_CACHE(0x61110000, 1M)
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}
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@ -0,0 +1,15 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Asami Doi <d0iasm.pub@gmail.com>.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <console/uart.h>
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#include <mainboard/addressmap.h>
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uintptr_t uart_platform_base(int idx)
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{
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return VIRT_UART_BASE;
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}
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